公开(公告)号：US06339551B1

公开(公告)日：2002-01-15

申请号：US09560514

申请日：2000-04-27

申请人： Simone Bartoli ,  Mauro Sali ,  Claudio Nava ,  Antonio Russo

发明人： Simone Bartoli ,  Mauro Sali ,  Claudio Nava ,  Antonio Russo

IPC分类号： G11C700

CPC分类号： G11C7/10 ,  G11C5/04 ,  G11C5/063 ,  G11C2207/105

摘要： A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.

摘要翻译： 半导体器件包括用于输入外部信号和/或用于输出来自所述半导体器件的信号的至少两个焊盘，至少两个非耦合缓冲器，每个至少两个非耦合缓冲器连接到每个所述焊盘，至少一个多路复用器通过 所述解耦缓冲器的装置和适于产生在所述多路复用器和所述非耦合缓冲器上操作的配置信号的至少一个存储元件，以选择性地使能所述焊盘中的一个或另一个。

公开(公告)号：US5848013A

公开(公告)日：1998-12-08

申请号：US824616

申请日：1997-03-27

申请人： Fabio Tassan Caser ,  Mauro Sali ,  Marcello Cane

发明人： Fabio Tassan Caser ,  Mauro Sali ,  Marcello Cane

IPC分类号： G11C8/10 ,  G11C16/08 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C16/08

摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.

摘要翻译： 本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号 和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子 矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。 耗尽晶体管的控制端构成电路的另一输入。

公开(公告)号：US5719807A

公开(公告)日：1998-02-17

申请号：US687257

申请日：1996-07-25

申请人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

发明人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

IPC分类号： G11C16/08 ,  G11C11/34

CPC分类号： G11C16/08

摘要： A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

公开(公告)号：US07761675B2

公开(公告)日：2010-07-20

申请号：US11432301

申请日：2006-05-10

申请人： Francesco Mastroianni ,  Antonino Mondello ,  Elena Cussotto ,  Massimiliano Mollichelli ,  Mauro Sali

发明人： Francesco Mastroianni ,  Antonino Mondello ,  Elena Cussotto ,  Massimiliano Mollichelli ,  Mauro Sali

IPC分类号： G06F12/00

CPC分类号： G11C16/22 ,  G06F12/1433 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/2022

摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.

摘要翻译： 闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路 第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。

公开(公告)号：US06912598B1

公开(公告)日：2005-06-28

申请号：US09627703

申请日：2000-07-28

申请人： Lorenzo Bedarida ,  Antonino Geraci ,  Mauro Sali ,  Simone Bartoli

发明人： Lorenzo Bedarida ,  Antonino Geraci ,  Mauro Sali ,  Simone Bartoli

IPC分类号： G11C16/10 ,  G11C16/26 ,  G06F9/28 ,  G06F13/16

CPC分类号： G11C16/10 ,  G11C16/26

摘要： An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

摘要翻译： 一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。 第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。 存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作 。

公开(公告)号：US06442068B1

公开(公告)日：2002-08-27

申请号：US09619589

申请日：2000-07-19

申请人： Simone Bartoli ,  Lorenzo Bedarida ,  Mauro Sali ,  Antonio Russo

发明人： Simone Bartoli ,  Lorenzo Bedarida ,  Mauro Sali ,  Antonio Russo

IPC分类号： G11C1134

CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C2216/20

摘要： An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

摘要翻译： 电可改变的半导体存储器包括至少两个存储器扇区，其内容是可单独改变的;以及控制电路，用于控制存储器内容的电气改变的操作，允许选择性地执行对内容的电气改变的操作 其中一个存储器扇区具有暂停执行以允许对另一个存储器扇区的读取访问的可能性。 控制电路还能够在暂停期间允许对其他存储器扇区的内容的突发模式或页面模式读取的操作。

公开(公告)号：US06349059B1

公开(公告)日：2002-02-19

申请号：US09716746

申请日：2000-11-20

申请人： Simone Bartoli ,  Antonio Geraci ,  Mauro Sali ,  Lorenzo Bedarida

发明人： Simone Bartoli ,  Antonio Geraci ,  Mauro Sali ,  Lorenzo Bedarida

IPC分类号： G11C1604

CPC分类号： G11C7/1033 ,  G11C7/1045 ,  G11C7/1072

摘要： A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.

摘要翻译： 一种用于从包括非易失性存储器矩阵的集成电子存储器件读取数据的方法包括向存储器提供要进行读取的存储器位置的地址，以随机读取模式访问存储器矩阵，提供存储器 具有时钟信号和地址确认信号（LAN），检测对突发读取模式存取的请求，以及当时钟信号显示上升沿时启动突发读取。 还提供了相关的电路。

公开(公告)号：US5999456A

公开(公告)日：1999-12-07

申请号：US943391

申请日：1997-10-03

申请人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

发明人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

IPC分类号： G11C16/08 ,  G11C11/34

CPC分类号： G11C16/08

摘要： A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

摘要翻译： 具有至少一个存储器扇区的闪存EEPROM。 存储器扇区包括多个存储单元的行和列; 至少一个负电压发生器，用于在用于擦除所述至少一个存储器扇区的存储器单元的擦除脉冲期间产生通常将所述多个行充电至负电位的负电压，以及在所述至少一个存储器扇区的开始处激活所述负电压发生器的控制逻辑 擦除脉冲并在擦除脉冲结束时使负电压发生器去激活。 闪存EEPROM，用于在擦除脉冲结束时控制至少一个存储器扇区的行的放电时间。

公开(公告)号：US5920505A

公开(公告)日：1999-07-06

申请号：US881713

申请日：1997-06-23

申请人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

发明人： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  G11C16/04

CPC分类号： G11C16/30

摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.

摘要翻译： 可在电可擦除半导体存储器件中集成的负字线电压调节电路。 电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。 电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供 用于调节负字线电压的调节电流。 运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。

公开(公告)号：US5784314A

公开(公告)日：1998-07-21

申请号：US679656

申请日：1996-07-12

申请人： Mauro Sali ,  Marco Dallabora ,  Marcello Carrera

发明人： Mauro Sali ,  Marco Dallabora ,  Marcello Carrera

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/50 ,  G11C11/34

CPC分类号： G11C16/3459 ,  G11C16/3454 ,  G11C29/028 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

摘要： A method for setting the threshold voltage of a reference memory cell of a memory device is described, the reference memory cell being used as a reference current generator for generating a reference current which is compared by a sensing circuit of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix of the memory device. The method comprises a first step in which the reference memory cell is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell is verified. The second step provides for performing a sensing of the reference memory cell using a memory cell with known threshold voltage belonging to the memory matrix as a reference current generator for generating a current which is compared by the sensing circuit with the current sunk by the reference memory cell.

摘要翻译： 描述了一种用于设置存储器件的参考存储单元的阈值电压的方法，该参考存储器单元用作参考电流发生器，用于产生参考电流，该参考电流由存储器件的感测电路与下降的电流进行比较 要被感测的存储器单元，属于存储器件的存储器矩阵。 该方法包括第一步骤，其中参考存储器单元被提交其阈值电压的改变，以及第二步骤，其中验证参考存储单元的阈值电压。 第二步骤是使用具有属于存储器矩阵的已知阈值电压的存储单元作为参考电流发生器来执行对参考存储单元的感测，用于产生电流，该电流由感测电路与当前由参考存储器 细胞。