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    Methods, apparatus, and instructions for converting vector data
    11.
    发明授权
    Methods, apparatus, and instructions for converting vector data 有权
    用于转换矢量数据的方法，装置和指令

    公开(公告)号：US08667250B2

    公开(公告)日：2014-03-04

    申请号：US11964631

    申请日：2007-12-26

    Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    IPC: G06F9/312

    CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

    Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

    Mechanism for effectively caching streaming and non-streaming data patterns
    14.
    发明授权
    Mechanism for effectively caching streaming and non-streaming data patterns 有权
    有效缓存流和非流数据模式的机制

    公开(公告)号：US08065488B2

    公开(公告)日：2011-11-22

    申请号：US12908183

    申请日：2010-10-20

    Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    IPC: G06F12/12

    CPC classification number: G06F12/127 ,  G06F12/0862 ,  G06F12/124 ,  G06F2212/6028

    Abstract: A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

    Abstract translation: 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。

    Unaligned memory operands
    16.
    发明授权
    Unaligned memory operands 有权
    未对齐的内存操作数

    公开(公告)号：US06721866B2

    公开(公告)日：2004-04-13

    申请号：US10029367

    申请日：2001-12-21

    Applicant: Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

    Inventor： Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

    IPC: G06F1204

    CPC classification number: G06F9/30043

    Abstract: A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand from the memory device, the second operand having part of the operand specified by the instruction, shifting the second operand by a second shift amount, and combining the first shifted data entry and the second shifted data entry to produce an aligned operand, wherein shifting the first operand and shifting the second operand is performed by a shifter also used for floating point functions.

    Abstract translation: 从存储装置获取操作数的方法包括从存储装置中的第一位置读取第一操作数，第一操作数包括由指令指定的操作数的一部分，将第一操作数移位第一移位量，读第二操作数 来自存储器件的数据操作数，第二操作数具有由指令指定的操作数的一部分，将第二操作数移位第二移位量，并组合第一移位数据条目和第二移位数据条目以产生对准的操作数，其中 移动第一操作数并移动第二操作数由也用于浮点函数的移位器执行。

    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA
    17.
    发明申请
    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA 审中-公开
    用于转换矢量数据的方法，装置和说明

    公开(公告)号：US20140019720A1

    公开(公告)日：2014-01-16

    申请号：US13762220

    申请日：2013-02-07

    Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    IPC: G06F9/30

    CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

    Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

    Partition-free multi-socket memory system architecture
    18.
    发明授权
    Partition-free multi-socket memory system architecture 有权
    无分区多插槽内存系统架构

    公开(公告)号：US08605099B2

    公开(公告)日：2013-12-10

    申请号：US12059193

    申请日：2008-03-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G06F13/00

    CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

    Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

    Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。

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