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    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
    12.
    发明申请
    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE 审中-公开
    在记忆体设备中的篡改检测和响应

    公开(公告)号：US20150356322A1

    公开(公告)日：2015-12-10

    申请号：US14832495

    申请日：2015-08-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G06F21/79 ,  G06F21/60 ,  G11C11/16

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作，产生模拟电流以仿真在正常操作期间预期的电流，以及擦除存储在存储器件上的数据。

    Tamper detection and response in a memory device
    13.
    发明授权
    Tamper detection and response in a memory device 有权
    存储设备中的防篡改检测和响应

    公开(公告)号：US09569640B2

    公开(公告)日：2017-02-14

    申请号：US14832495

    申请日：2015-08-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C5/14 ,  G06F21/79 ,  G11C7/24 ,  G11C11/16 ,  G06F21/60 ,  G11C13/00

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，在存储器装置上的响应包括禁用一个或多个存储器操作，产生模拟电流以模拟在正常操作期间预期的电流，以及擦除存储在存储器件上的数据。

    Boosted supply voltage generator for a memory device and method therefore
    14.
    发明授权
    Boosted supply voltage generator for a memory device and method therefore 有权
    因此，用于存储器件的升压电源电压发生器和方法

    公开(公告)号：US09361964B1

    公开(公告)日：2016-06-07

    申请号：US15051794

    申请日：2016-02-24

    Applicant: Everspin Technologies, Inc.

    Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

    Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

    Memory Device With Timing Overlap Mode
    15.
    发明申请
    Memory Device With Timing Overlap Mode 审中-公开
    具有定时重叠模式的存储器

    公开(公告)号：US20160104518A1

    公开(公告)日：2016-04-14

    申请号：US14973884

    申请日：2015-12-18

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

    IPC: G11C7/12

    CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

    Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
    17.
    发明申请
    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE 有权
    在记忆体设备中的篡改检测和响应

    公开(公告)号：US20140226396A1

    公开(公告)日：2014-08-14

    申请号：US14175337

    申请日：2014-02-07

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G11C7/24 ,  G11C11/16

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作并产生模拟电流以仿真在正常操作期间预期的电流。

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