公开(公告)号：US10573365B2

公开(公告)日：2020-02-25

申请号：US16251882

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16 ,  G06F11/10 ,  G11C11/4094 ,  G11C7/12 ,  G11C8/08 ,  G11C8/14

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

公开(公告)号：US10269405B2

公开(公告)日：2019-04-23

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/0804

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US10146601B2

公开(公告)日：2018-12-04

申请号：US14297386

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Jon Slaughter ,  Dimitri Houssameddine ,  Thomas Andre ,  Syed M. Alam

IPC: G06F11/00 ,  G06F11/07 ,  G11C11/16

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

公开(公告)号：US10141039B2

公开(公告)日：2018-11-27

申请号：US14495083

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G06F12/08 ,  G11C11/16 ,  G06F12/0806 ,  G06F12/0879 ,  G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

公开(公告)号：US10037790B2

公开(公告)日：2018-07-31

申请号：US15452831

申请日：2017-03-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16 ,  G11C7/12 ,  G11C7/08 ,  G06F12/0806 ,  G06F12/0879 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

公开(公告)号：US09881695B2

公开(公告)日：2018-01-30

申请号：US15356223

申请日：2016-11-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US09870812B2

公开(公告)日：2018-01-16

申请号：US15370114

申请日：2016-12-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C7/00 ,  G11C11/16 ,  G11C7/12 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G11C11/4076

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

公开(公告)号：US09691442B2

公开(公告)日：2017-06-27

申请号：US14667888

申请日：2015-03-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Dietmar Gogl

IPC: G11C7/02 ,  G11C5/14 ,  G11C16/12 ,  G11C16/30 ,  G11C7/06 ,  G11C8/12 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C16/12 ,  G11C16/30

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

公开(公告)号：US20170178709A1

公开(公告)日：2017-06-22

申请号：US15452831

申请日：2017-03-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

公开(公告)号：US20170104498A1

公开(公告)日：2017-04-13

申请号：US15385130

申请日：2016-12-20

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.