公开(公告)号：US09431294B2

公开(公告)日：2016-08-30

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US09236299B2

公开(公告)日：2016-01-12

申请号：US14201255

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

公开(公告)号：US20140217588A1

公开(公告)日：2014-08-07

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

公开(公告)号：US09666524B2

公开(公告)日：2017-05-30

申请号：US15098513

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung Chae ,  Larry Zhao

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

公开(公告)号：US09362228B2

公开(公告)日：2016-06-07

申请号：US14059498

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung Chae ,  Larry Zhao

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

Abstract translation: 提供了在通孔的侧壁和底部上形成阻挡层的方法以及所得到的器件。 实施例包括在基板中形成金属线; 在金属线和基板上形成Si基绝缘层; 在所述Si基绝缘层中形成通孔至所述金属线; 在通孔的侧壁和底表面上形成双层Mn / MnN; 并用金属填充通孔。

公开(公告)号：US20160118292A1

公开(公告)日：2016-04-28

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US09318436B2

公开(公告)日：2016-04-19

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US09087881B2

公开(公告)日：2015-07-21

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming He ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US20150108647A1

公开(公告)日：2015-04-23

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。