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    PROBE FOR PIC DIE WITH RELATED TEST ASSEMBLY AND METHOD
    11.
    发明申请
    PROBE FOR PIC DIE WITH RELATED TEST ASSEMBLY AND METHOD 审中-公开

    公开(公告)号：US20200049737A1

    公开(公告)日：2020-02-13

    申请号：US16100297

    申请日：2018-08-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ye Wang ,  Hanyi Ding ,  Timothy M. Platt

    IPC: G01R1/073 ,  G01R1/067

    Abstract: Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.

    Apparatus and method for vector s-parameter measurements
    12.
    发明授权
    Apparatus and method for vector s-parameter measurements 有权

    公开(公告)号：US10379191B2

    公开(公告)日：2019-08-13

    申请号：US15868248

    申请日：2018-01-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Adem G. Aydin ,  Hanyi Ding

    IPC: G01R35/00 ,  G01R27/28 ,  G01R27/02

    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.

    DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER
    15.
    发明申请
    DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER 审中-公开
    具有高电阻手柄波纹的绝缘子硅基板的器件结构

    公开(公告)号：US20160372582A1

    公开(公告)日：2016-12-22

    申请号：US14745704

    申请日：2015-06-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

    IPC: H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

    CPC classification number: H01L29/0821 ,  H01L21/762 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7371

    Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

    Abstract translation: 使用包括高电阻处理晶片的绝缘体上硅衬底形成器件结构和器件结构的方法。 在高电阻处理晶片中形成掺杂区域。 形成第一沟槽，其延伸穿过绝缘体上硅衬底的器件层和掩埋绝缘体层到高电阻处理晶片。 掺杂区域包括在第一沟槽横向延伸的掺杂区域的横向延伸。 半导体层在第一沟槽内外延生长，并且使用半导体层的至少一部分形成器件结构。 形成第二沟槽，其延伸穿过器件层和掩埋绝缘体层到掺杂区域的横向延伸，并且在第二沟槽中形成导电插塞。 掺杂区域和插塞包括身体接触。

    Wafer thinning endpoint detection for TSV technology
    16.
    发明授权
    Wafer thinning endpoint detection for TSV technology 有权
    TSV技术的晶圆薄化端点检测

    公开(公告)号：US09349661B2

    公开(公告)日：2016-05-24

    申请号：US14161738

    申请日：2014-01-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hanyi Ding ,  Oleg Gluschenkov ,  Ping-Chuan Wang ,  Lin Zhou

    IPC: H01L21/78 ,  H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/26 ,  H01L21/30625 ,  H01L21/76898 ,  H01L22/14

    Abstract: Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through silicon via (TSV) structures formed in the wafer. A specially made wafer handle is bonded to the wafer. Conductive slurry is used in the wafer backside thinning process. The wafer handle provides electrical connectivity to an electrical measurement tool, and conductive posts in the wafer handle are proximal to a test structure on the wafer. A plurality of electrically isolated TSVs is monitored via the electrical measurement tool. When the TSVs are exposed on the backside as a result of thinning, the conductive slurry shorts the electrically isolated TSVs, changing the electrical properties of the plurality of TSVs. The change in electrical properties is detected and used to trigger termination of the wafer backside thinning process.

    Abstract translation: 本发明的实施例提供了一种用于晶片薄化端点检测的装置和方法。 本发明的实施例利用在晶片中形成的硅通孔（TSV）结构。 特殊制造的晶圆把手与晶片结合。 导电浆料用于晶片背面变薄处理。 晶片手柄提供与电测量工具的电连接，并且晶片把手中的导电柱靠近晶片上的测试结构。 通过电测量工具监测多个电隔离TSV。 当TSV由于变薄而暴露在背面时，导电浆料使电隔离的TSV短路，改变多个TSV的电性能。 检测电特性的变化并用于触发晶圆背面变薄过程的终止。

    Separation of integrated circuit structure from adjacent chip
    17.
    发明授权
    Separation of integrated circuit structure from adjacent chip 有权

    公开(公告)号：US10256204B2

    公开(公告)日：2019-04-09

    申请号：US15345608

    申请日：2016-11-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Glen E Richard ,  Stephen P Ayotte ,  Hanyi Ding

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/34

    Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

    INDUCTOR STRUCTURE HAVING EMBEDDED AIRGAP
    20.
    发明申请
    INDUCTOR STRUCTURE HAVING EMBEDDED AIRGAP 审中-公开

    公开(公告)号：US20160012952A1

    公开(公告)日：2016-01-14

    申请号：US14864191

    申请日：2015-09-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hanyi Ding ,  Anthony K. Stamper

    IPC: H01F27/00 ,  H01F27/28

    CPC classification number: H01F27/006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/004 ,  H01F2027/2819

    Abstract: Various embodiments include inductor structures including at least one air gap for reducing capacitance between windings in the inductor structure. One embodiment includes an inductor structure having: a substrate; an insulation layer overlying the substrate; a conductive winding overlying the substrate within the insulation layer, the conductive winding wrapped around itself to form a plurality of turns substantially concentric about a central axis; an insulating structural support containing an air gap between the conductive winding and the insulation layer, the insulating structural support at least one of under, over or surrounding the plurality of turns of the conductive winding or between adjacent turns in the conductive winding; and at least one insulation pocket located radially inside a radially innermost turn in the plurality of turns with respect to the central axis.

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