公开(公告)号：US09275874B2

公开(公告)日：2016-03-01

申请号：US14015640

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/321

CPC classification number: H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

Abstract translation: 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US20150325622A1

公开(公告)日：2015-11-12

申请号：US14272916

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract translation: 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。

公开(公告)号：US09076846B2

公开(公告)日：2015-07-07

申请号：US14071070

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。 当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。 此外，该方法包括修改第一暴露表面以形成修改的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到经修改的第一暴露表面和第二暴露表面。

公开(公告)号：US20150064903A1

公开(公告)日：2015-03-05

申请号：US14015640

申请日：2013-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc.

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC: H01L21/306

CPC classification number: H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

Abstract translation: 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US20140220775A1

公开(公告)日：2014-08-07

申请号：US13757504

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

Abstract: A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.

Abstract translation: 一种用于制造集成电路的方法包括在氧化物层上提供包括保护层的衬底，并蚀刻通过保护层的凹陷并进入氧化物层。 阻挡材料沉积在衬底上以形成包含凹部中的第一区域和凹部外部的第二区域的阻挡层。 导电材料沉积在阻挡层上并在凹槽中形成嵌入的电互连，并且在凹部外部形成覆盖层。 去除导电材料的覆盖层区域，并且嵌入式电互连件的一部分凹陷。 此后，蚀刻阻挡层以去除阻挡层的第二区域并使阻挡层的第一区域的一部分凹陷。 在蚀刻阻挡层之后，从氧化物层去除保护层。

公开(公告)号：US09318437B1

公开(公告)日：2016-04-19

申请号：US14611740

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming He ,  Kunaljeet Tanwar

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/321 ,  H01L23/00

CPC classification number: H01L23/53238 ,  H01L21/3105 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/26 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinner barrier/liner stack for vias and metal lines and the resulting device are disclosed. Embodiments include forming a via through an interlayer dielectric (ILD) and capping layer, down to a first metal layer; forming a moisture scavenging layer precursor over the ILD and on side and bottom surfaces of the via; annealing the moisture scavenging layer precursor, forming a moisture scavenging layer; forming a barrier/liner stack over the moisture scavenging layer; and depositing a second metal layer over the barrier/liner stack and filling the via and trench.

Abstract translation: 公开了形成用于通孔和金属线的较薄阻挡层/衬垫叠层的方法以及所得到的器件。 实施例包括通过层间电介质（ILD）和覆盖层形成通孔，向下到第一金属层; 在ILD上和通孔的侧表面和底表面上形成除湿层前体; 退火除湿层前体，形成除湿层; 在水分清除层上形成阻挡层/衬垫层; 以及在所述阻挡层/衬垫叠层上沉积第二金属层并填充所述通孔和沟槽。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

公开(公告)号：US20150126028A1

公开(公告)日：2015-05-07

申请号：US14071070

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES, Inc

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar ,  Xunyuan Zhang

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。 当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。 此外，该方法包括修改第一暴露表面以形成修饰的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到修饰的第一暴露表面和第二暴露表面。

公开(公告)号：US08835306B2

公开(公告)日：2014-09-16

申请号：US13757504

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

Abstract: A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.

Abstract translation: 一种用于制造集成电路的方法包括在氧化物层上提供包括保护层的衬底，并蚀刻通过保护层的凹陷并进入氧化物层。 阻挡材料沉积在衬底上以形成包含凹部中的第一区域和凹部外部的第二区域的阻挡层。 导电材料沉积在阻挡层上并在凹槽中形成嵌入的电互连，并且在凹部外部形成覆盖层。 去除导电材料的覆盖层区域，并且嵌入式电互连件的一部分凹陷。 此后，蚀刻阻挡层以去除阻挡层的第二区域并使阻挡层的第一区域的一部分凹陷。 在蚀刻阻挡层之后，从氧化物层去除保护层。