公开(公告)号：US09698241B1

公开(公告)日：2017-07-04

申请号：US15071600

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Suraj K. Patil ,  Min-Hwa Chi ,  Mitsuhiro Togo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

公开(公告)号：US09659862B1

公开(公告)日：2017-05-23

申请号：US14936582

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L29/02 ,  H01L47/00 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US20160163824A1

公开(公告)日：2016-06-09

申请号：US14560054

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dong-Woon Shin ,  Min-Hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实例中，一种用于制造集成电路的方法包括在与半导体衬底上的虚拟栅极结构相邻的侧壁上形成侧壁间隔结构。 另外的侧壁间隔结构横向邻近侧壁间隔结构形成，并在侧壁间隔结构的下部形成。 虚拟栅极结构被替换为栅极结构。

公开(公告)号：US20160071979A1

公开(公告)日：2016-03-10

申请号：US14476830

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L29/16 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.

Abstract translation: 一种方法包括在限定在半导体衬底上的翅片上形成离子注入层。 将半导体衬底退火以将离子注入层转换成电介质层。 在形成离子注入层之后的沟道区域中，在鳍的上方形成栅电极结构。 鳍片凹陷在源极/漏极区域中。 在源极/漏极区域中外延生长半导体材料。

公开(公告)号：US20190088742A1

公开(公告)日：2019-03-21

申请号：US15709671

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/0847 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76895 ,  H01L27/088 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/785

Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer formed adjacent the first gate structure, and first conductive source/drain contact structures positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first portion of the first conductive source/drain contact structures is recessed at a first axial position along the first gate structure to define a first cavity. A second portion of the first conductive source/drain contact structures is recessed at a second axial position along the gate structure to define a second cavity. A dielectric cap layer is formed in the first and second cavities. A first conductive contact contacting the first gate structure in the first axial position is formed.

公开(公告)号：US09337340B2

公开(公告)日：2016-05-10

申请号：US14656649

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-Hwa Chi ,  Hoong Shing Wong

IPC: H01L29/78 ,  H01L29/22 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.

公开(公告)号：US09331159B1

公开(公告)日：2016-05-03

申请号：US14615470

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Yan Ping Shen ,  Wei Hua Tong ,  Haiting Wang ,  Min-Hwa Chi

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L21/02233 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract translation: 提供了制造具有至少部分成角度的上表面的具有凸起的有源区域的晶体管的方法。 该方法包括例如：提供设置在衬底上的栅极结构，所述栅极结构包括共形间隔层; 形成邻接所述共形间隔层的侧壁的凸起的有源区; 在凸起的活动区域上提供保护材料; 选择性地蚀刻保形间隔层的侧壁，将凸起的有源区域的侧部暴露在保护材料下方; 并且蚀刻凸起的有源区域的暴露的侧部分以部分地切割保护材料，其中蚀刻有助于至少部分地限定晶体管的凸起的有源区的至少部分成角度的上表面。

公开(公告)号：US20190296108A1

公开(公告)日：2019-09-26

申请号：US16437440

申请日：2019-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66

Abstract: A device includes a first gate structure positioned above an active region defined in a semiconducting substrate. A first spacer is positioned adjacent the first gate structure. First conductive source/drain contact structures are positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first recessed portion of the first conductive source/drain contact structures is positioned at a first axial position along the first gate structure. A second recessed portion of the first conductive source/drain contact structures is positioned at a second axial position along the gate structure. A dielectric cap layer is positioned above the first and second recessed portions. A first conductive contact contacts the first gate structure in the first axial position. The dielectric cap layer above the first recessed portion is positioned adjacent the first conductive contact.

公开(公告)号：US10396155B2

公开(公告)日：2019-08-27

申请号：US15709671

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/768 ,  H01L29/78

Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer formed adjacent the first gate structure, and first conductive source/drain contact structures positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first portion of the first conductive source/drain contact structures is recessed at a first axial position along the first gate structure to define a first cavity. A second portion of the first conductive source/drain contact structures is recessed at a second axial position along the gate structure to define a second cavity. A dielectric cap layer is formed in the first and second cavities. A first conductive contact contacting the first gate structure in the first axial position is formed.

公开(公告)号：US10121893B2

公开(公告)日：2018-11-06

申请号：US15797634

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49 ,  H01L27/11

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.