公开(公告)号：US09418899B1

公开(公告)日：2016-08-16

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping Shen ,  Min-hwa Chi ,  Xusheng Wu ,  Weihua Tong ,  Haiting Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直放置第二Ti层中的Al或C; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US09698269B2

公开(公告)日：2017-07-04

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L21/321 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US09331159B1

公开(公告)日：2016-05-03

申请号：US14615470

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Yan Ping Shen ,  Wei Hua Tong ,  Haiting Wang ,  Min-Hwa Chi

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L21/02233 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract translation: 提供了制造具有至少部分成角度的上表面的具有凸起的有源区域的晶体管的方法。 该方法包括例如：提供设置在衬底上的栅极结构，所述栅极结构包括共形间隔层; 形成邻接所述共形间隔层的侧壁的凸起的有源区; 在凸起的活动区域上提供保护材料; 选择性地蚀刻保形间隔层的侧壁，将凸起的有源区域的侧部暴露在保护材料下方; 并且蚀刻凸起的有源区域的暴露的侧部分以部分地切割保护材料，其中蚀刻有助于至少部分地限定晶体管的凸起的有源区的至少部分成角度的上表面。

公开(公告)号：US09312145B2

公开(公告)日：2016-04-12

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L21/469 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US09202697B2

公开(公告)日：2015-12-01

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying Luo ,  Feng Zhou ,  Yan Ping Shen ,  Haiting Wang ,  Haoran Shi ,  Wei Hua Tong ,  Seung Kim ,  Yong Meng Lee

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。