公开(公告)号：US20200051923A1

公开(公告)日：2020-02-13

申请号：US16654354

申请日：2019-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/027 ,  G03F7/16

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

公开(公告)号：US09576894B2

公开(公告)日：2017-02-21

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09362162B2

公开(公告)日：2016-06-07

申请号：US14459444

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Teck Jung Tang ,  Mark Alexander Zaleski

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).

Abstract translation: 提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。 该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及 施加减小一个开口的纵横比的能量。 在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

公开(公告)号：US10784119B2

公开(公告)日：2020-09-22

申请号：US16154306

申请日：2018-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hsueh-Chung Chen ,  Steven McDermott ,  Martin O'Toole ,  Brendan O'Brien ,  Terry A. Spooner

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

公开(公告)号：US20190079408A1

公开(公告)日：2019-03-14

申请号：US15698775

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sohan Singh Mehta ,  Mark C. Duggan ,  Sunil Kumar Singh ,  Robert Justin Morgan ,  SherJang Singh ,  Ravi Prakash Srivastava ,  Craig D. Higgins ,  Jason L. Behnke ,  Vineet Sharma

IPC: G03F7/32

Abstract: The disclosure is directed to a method for lithographic patterning. The method may include: exposing a photoresist to a radiant energy; developing the photoresist in a first developer, thereby creating an opening within the photoresist including sidewalls having a slant; and developing the photoresist in a second developer immediately after the developing of the photoresist in the first developer, thereby reducing the slant of the sidewalls of the opening. Where the photoresist is a positive tone development (PTD) photoresist, the first developer may include a positive developer, and the second developer may include a negative developer. Where the photoresist is a negative tone development (NTD) photoresist, the first developer may include a negative developer, and the second developer may include a positive developer.

公开(公告)号：US10192780B1

公开(公告)日：2019-01-29

申请号：US15991529

申请日：2018-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaohan Wang ,  Jiehui Shu ,  Brendan O'Brien ,  Terry A. Spooner ,  Jinping Liu ,  Ravi Prakash Srivastava

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning. A mandrel line including an upper layer and a lower layer is formed over a hardmask. A non-mandrel cut block is formed over a portion of a non-mandrel line, after which the upper layer of the mandrel line is removed. An etch mask is formed over a first section of the lower layer of the mandrel line defining a mandrel cut block over a first portion of the hardmask. The first section of the lower layer is arranged between adjacent second sections of the lower layer. The second sections of the lower layer of the mandrel line are removed to expose respective second portions of the hardmask, and the second portions of the hardmask are removed to form a trench. The mandrel cut block masks the first portion of the hardmask during the etching process.