公开(公告)号：US10770344B2

公开(公告)日：2020-09-08

申请号：US16244071

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuping Ren ,  Haigou Huang ,  Ravi Prakash Srivastava ,  Zhiguo Sun ,  Qiang Fang ,  Cheng Xu ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

公开(公告)号：US10692812B2

公开(公告)日：2020-06-23

申请号：US15980085

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hui Zang ,  Jiehui Shu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

公开(公告)号：US20190355658A1

公开(公告)日：2019-11-21

申请号：US15980085

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hui Zang ,  Jiehui Shu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

公开(公告)号：US20160358851A1

公开(公告)日：2016-12-08

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US20200111677A1

公开(公告)日：2020-04-09

申请号：US16154306

申请日：2018-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hsueh-Chung Chen ,  Steven McDermott ,  Martin O'Toole ,  Brendan O'Brien ,  Terry A. Spooner

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

公开(公告)号：US09691654B1

公开(公告)日：2017-06-27

申请号：US14978650

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Sohan Singh Mehta ,  Ravi Prakash Srivastava

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09613909B2

公开(公告)日：2017-04-04

申请号：US14824181

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Nicholas Robert Stokes

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20190267329A1

公开(公告)日：2019-08-29

申请号：US15904853

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: H01L23/544 ,  G03F9/00 ,  G03F7/16 ,  H01L21/027

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

公开(公告)号：US20190237356A1

公开(公告)日：2019-08-01

申请号：US15882465

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295

Abstract: Interconnect structures and methods for forming an interconnect structure. A dielectric layer of a metallization level is deposited and a trench is patterned in the dielectric layer. A sacrificial layer is formed in the trench in the dielectric layer. The sacrificial layer is patterned to form a first trench and a second trench separated from the first trench by a section of the sacrificial layer. A first metal interconnect is formed in the first trench, a second metal interconnect is formed in the second trench, and a porous cap layer is formed over the first metal interconnect, the second metal interconnect, and the section of the sacrificial layer. After forming the porous cap layer, the section of the sacrificial layer is removed.

公开(公告)号：US10833022B2

公开(公告)日：2020-11-10

申请号：US16654354

申请日：2019-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: G03F9/00 ,  G03F7/16 ,  G03F7/20 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528 ,  H01L23/538

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.