公开(公告)号：US20200035556A1

公开(公告)日：2020-01-30

申请号：US16047470

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10388602B2

公开(公告)日：2019-08-20

申请号：US15251804

申请日：2016-08-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

公开(公告)号：US10242867B2

公开(公告)日：2019-03-26

申请号：US15598393

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Vimal Kamineni

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49

Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

公开(公告)号：US20190013241A1

公开(公告)日：2019-01-10

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chane ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

公开(公告)号：US10134633B1

公开(公告)日：2018-11-20

申请号：US15791658

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Stan Tsai ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4757 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/417

Abstract: In a self-aligned contact (SAC) process, a sacrificial etch stop layer is embedded over source/drain regions, i.e., directly over an interlayer dielectric (IDL) disposed over source/drain regions to enable polishing of a nitride capping layer with respect to the interlayer dielectric. The sacrificial etch stop layer may comprise cobalt metal, and is adapted to be removed and replaced with additional ILD material after controlled polishing of the nitride capping layer.

公开(公告)号：US10026693B2

公开(公告)日：2018-07-17

申请号：US15589829

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Mark V. Raymond ,  Praneet Adusumilli ,  Chengyu Niu

IPC: H01L23/522 ,  H01L23/535 ,  H01L21/768 ,  H01L29/78 ,  H01L21/285 ,  H01L21/311 ,  H01L21/67 ,  H01L23/532 ,  H01L29/45

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

公开(公告)号：US09466676B2

公开(公告)日：2016-10-11

申请号：US14514422

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Ruilong Xie

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract translation: 提供了形成具有栅极金属凹部的半导体器件（例如，诸如FinFET或平面器件的晶体管）的方法。 在一种方法中，将衬垫层和金属层（例如，W）施加在沟槽（例如，经由CVD和/或ALD）中。 然后，将使用单个室（例如，极端填充室）来单独地蚀刻衬里层和金属层。 通常，衬里层可以比金属层更深地被回蚀以提供较大的接触和较低的电阻。 蚀刻完成后，将执行金属（例如W）的自底向上填充/生长（例如，通过在W室等中的CVD）以增加沟槽中的栅极金属的存在。

公开(公告)号：US20140327140A1

公开(公告)日：2014-11-06

申请号：US13887174

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

公开(公告)号：US10854515B2

公开(公告)日：2020-12-01

申请号：US16778884

申请日：2020-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10468300B2

公开(公告)日：2019-11-05

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.