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    FDSOI semiconductor device with contact enhancement layer and method of manufacturing
    11.
    发明授权
    FDSOI semiconductor device with contact enhancement layer and method of manufacturing 有权

    公开(公告)号：US10347543B2

    公开(公告)日：2019-07-09

    申请号：US15810557

    申请日：2017-11-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

    Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

    METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY
    13.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY 有权
    用于SOI技术的混合图书跟踪设计的方法，装置和系统

    公开(公告)号：US20170076031A1

    公开(公告)日：2017-03-16

    申请号：US15047878

    申请日：2016-02-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anurag Mittal ,  Mahbub Rashed

    IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528 ,  H01L27/12

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H01L21/84 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1203

    Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

    Abstract translation: 所公开的至少一种方法，装置和系统涉及提供用于制造半导体器件的设计。 具有第一宽度的第一功能单元被放置在电路布局上。 确定第一功能单元的至少一个晶体管是正向偏置还是反向偏置。 具有第二宽度的第二功能单元被布置在电路布局上与第一功能单元相邻，以响应于确定至少一个晶体管将在第一和第二功能单元的总宽度内提供第一偏置阱 正向偏向或反向偏向。

    Forming a low votage antifuse device and resulting device
    14.
    发明授权
    Forming a low votage antifuse device and resulting device 有权
    形成低投票反熔丝装置和结果装置

    公开(公告)号：US09177963B2

    公开(公告)日：2015-11-03

    申请号：US14082263

    申请日：2013-11-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Anurag Mittal ,  Marc Tarabbia

    IPC: H01L27/112 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/11206 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

    Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.

    Abstract translation: 公开了低压反熔丝装置的方法和所得装置。 实施例可以包括在基板上形成多个翅片，去除鳍片的一部分，形成翅片尖端，在至少鳍片尖端上形成栅极氧化物层的第一区域，形成上面的栅极氧化物层的第二区域 所述多个翅片的剩余部分，其中所述第一区域比所述第二区域薄，并且在至少所述翅片末端上形成栅极以形成反熔丝一次性可编程装置。

    PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS)
    16.
    发明申请
    PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS) 有权
    基于优先级的布局VERSUS SCHEMATIC（LVS）

    公开(公告)号：US20140282330A1

    公开(公告)日：2014-09-18

    申请号：US13837763

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Niladri MOJUMDER ,  Bipul Paul ,  Anurag Mittal ,  Juengling Werner

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5072

    Abstract: An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.

    Abstract translation: 公开了一种用于方法的方法和相关系统，其使得能够对设备，电路和感兴趣的模块进行优先级排序。 实施例包括：确定指示IC设计的物理布局的电性能的第一电气布局，所述第一电气布局指示所述物理布局的多个设备; 基于所述设备的一个或多个连接来选择所述多个设备的子集; 以及生成指示所述物理布局的电性能的第二电气布局，所述第二电气布局指示所选择的设备，而不包括所述多个设备中的至少一个。

    Integrated circuit with semiconductor fin fuse
    18.
    发明授权
    Integrated circuit with semiconductor fin fuse 有权
    集成电路与半导体鳍片保险丝

    公开(公告)号：US09219040B2

    公开(公告)日：2015-12-22

    申请号：US14032484

    申请日：2013-09-20

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

    IPC: H01L23/525 ,  H01L23/62

    CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

    Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

    DECOUPLING CAPACITOR FOR SEMICONDUCTORS
    19.
    发明申请
    DECOUPLING CAPACITOR FOR SEMICONDUCTORS 审中-公开
    用于半导体的解耦电容器

    公开(公告)号：US20150364426A1

    公开(公告)日：2015-12-17

    申请号：US14303714

    申请日：2014-06-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Jerome Ciavatti ,  Anurag Mittal ,  Manfred Eller

    IPC: H01L23/538 ,  H01L23/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L27/08

    CPC classification number: H01L27/0629 ,  H01L27/0805 ,  H01L29/94

    Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.

    Abstract translation: 本发明的实施例提供了一种改进的去耦电容器结构。 接触区域设置在去耦电容器结构的源极/漏极区域上。 每个接触区域形成为多个段，其中段间间隙将多个段中的段与多个段的相邻段分离。 实施例可以包括两个栅极区域之间的多个接触区域。 去耦电容器的阵列可以被布置为P阱和N阱结构的交替“棋盘”图案，并且可以以与金属化层对角的角度定向，以便于阵列内的多个去耦电容器的连接。

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