公开(公告)号：US10396084B1

公开(公告)日：2019-08-27

申请号：US15944910

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare ,  Hongsik Yoon

IPC: H01L21/027 ,  H01L27/11 ,  H01L21/033 ,  H01L21/308

Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

公开(公告)号：US10340359B2

公开(公告)日：2019-07-02

申请号：US15889321

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L29/51 ,  H01L21/308 ,  H01L21/306 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L21/3213

Abstract: A high-k dielectric metal gate (HKMG) transistor includes a substrate, an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. A first liner contacts a sidewall portion of the upper portion. A spacer contacts the first liner and a sidewall portion of the lower portion. Raised source and drain regions are positioned adjacent the spacer. A height of the uppermost surface of the spacer is greater than a height of an uppermost surface of the raised source and drain regions. A width of the upper portion between the raised source and drain regions is smaller than a width of the lower portion between the raised source and drain regions.

公开(公告)号：US10304683B2

公开(公告)日：2019-05-28

申请号：US15845340

申请日：2017-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/66 ,  H01L21/285 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

Abstract: By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.

公开(公告)号：US20190043752A1

公开(公告)日：2019-02-07

申请号：US15670465

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Michael Zier

IPC: H01L21/762

Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

公开(公告)号：US10177163B1

公开(公告)日：2019-01-08

申请号：US15895053

申请日：2018-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith

IPC: H01L23/02 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/10 ,  H01L27/11558 ,  H01L21/762 ,  H01L29/66 ,  H01L29/788 ,  H01L27/12 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/266

Abstract: One illustrative device disclosed a floating gate capacitor located in and above a first region of an SOI substrate located on a first side of an isolation trench and a transistor device located in and above a second region of the SOI substrate that is on the opposite side of the isolation trench. The device also includes a control gate formed in the bulk semiconductor layer in the first region and a gate structure that extends across the isolation trench and above the first and second regions. A first portion of the gate structure is positioned above the first region and the control gate and a second portion of the gate structure is positioned above the second region, wherein the first portion of the gate structure constitutes a floating gate for the floating gate capacitor and the second portion of the gate structure constitutes a transistor gate structure for the transistor device.

公开(公告)号：US20180053829A1

公开(公告)日：2018-02-22

申请号：US15242689

申请日：2016-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sylvain Henri Baudot ,  Peter Javorka ,  Gerd Zschaetzsch

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/66628 ,  H01L29/786

Abstract: A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate structure, the raised source/drain regions being formed at opposing sides of the shaped gate structure relative to a length direction of the shaped gate structure, wherein the gate electrode has a tapering shape according to which a dimension of the gate electrode along the length direction varies from a maximum value at a lower portion of the gate electrode close to the gate dielectric layer towards a minimal value at a top portion of the gate electrode.

公开(公告)号：US09698179B2

公开(公告)日：2017-07-04

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

公开(公告)号：US20170040450A1

公开(公告)日：2017-02-09

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract translation: 本公开根据一些说明性实施例提供了一种形成半导体器件的方法，所述方法包括提供SOI衬底，所述SOI衬底具有设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基底衬底材料 在所述SOI衬底的有源区中的所述有源半导体层上形成栅极结构，在所述栅极结构形成之后，部分地露出所述基底以形成至少一个本体暴露区域，以及形成用于使所述至少一个 体积暴露区域。

公开(公告)号：US20190131133A1

公开(公告)日：2019-05-02

申请号：US15845340

申请日：2017-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/66 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L21/285

Abstract: By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.

公开(公告)号：US10199259B1

公开(公告)日：2019-02-05

申请号：US15670465

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Michael Zier

IPC: H01L21/308 ,  H01L21/762 ,  G03F7/00 ,  G03F7/20 ,  G03F1/00

Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.