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    OVERLAY STRUCTURES
    13.
    发明申请
    OVERLAY STRUCTURES 审中-公开

    公开(公告)号：US20190206802A1

    公开(公告)日：2019-07-04

    申请号：US15860775

    申请日：2018-01-03

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xintuo DAI ,  Dongsuk PARK ,  Guoxiang NING ,  Mert KARAKOY

    IPC: H01L23/544 ,  H01L21/66

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.

    METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF
    15.
    发明申请
    METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF 有权

    公开(公告)号：US20160196381A1

    公开(公告)日：2016-07-07

    申请号：US15071890

    申请日：2016-03-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guoxiang NING ,  Guido UEBERREITER ,  Llyod C. LITT ,  Paul ACKMANN

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

    Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

    ACHIEVING A CRITICAL DIMENSION TARGET BASED ON RESIST CHARACTERISTICS
    16.
    发明申请
    ACHIEVING A CRITICAL DIMENSION TARGET BASED ON RESIST CHARACTERISTICS 有权
    基于电阻特性实现关键尺寸目标

    公开(公告)号：US20160125121A1

    公开(公告)日：2016-05-05

    申请号：US14533497

    申请日：2014-11-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

    IPC: G06F17/50 ,  G03F7/34 ,  G03F7/32 ,  G03F7/16 ,  G03F7/20

    CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

    Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

    Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。

    OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
    17.
    发明申请
    OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION 有权
    叠加标记依赖DUMMY填充以缓解门高度变化

    公开(公告)号：US20150287651A1

    公开(公告)日：2015-10-08

    申请号：US14243491

    申请日：2014-04-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guoxiang NING ,  Chan Seob CHO ,  Paul ACKMANN ,  Jung Yu HSIEH ,  Hui Peng KOH

    IPC: H01L21/66 ,  H01L21/306 ,  H01L27/088 ,  H01L23/544

    CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

    Abstract translation: 提供了基于覆盖标记的形状和所得到的装置在有源层区域上形成虚拟结构和覆盖标记保护区域的方法。 实施例包括确定重叠标记的尺寸和形状; 基于覆盖标记的形状确定覆盖标记保护区的大小和形状; 基于重叠标记的形状确定多个虚拟结构的形状; 基于覆盖标记和多个虚拟结构的尺寸和形状来确定活动层区域的尺寸和形状; 在半导体衬底的有源层中形成有源层区; 在所述半导体衬底的多晶硅层中的所述有源层区域上形成所述覆盖标记和所述多个虚设结构; 并平坦化多层。

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