公开(公告)号：US09443871B2

公开(公告)日：2016-09-13

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L29/417 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。

公开(公告)号：US20160260606A1

公开(公告)日：2016-09-08

申请号：US14635071

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/033 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/665

Abstract: The present disclosure provides methods of forming a masking pattern and a semiconductor device structure, wherein printed half pitches of, for example, about 20 nm or less may be formed. A method of forming a masking pattern is provided wherein an unpatterned mask layer is formed over a semiconductor device structure provided in and on an upper surface of a semiconductor substrate, and the unpatterned mask layer is patterned for forming the masking pattern over the semiconductor device structure. The unpatterned mask layer is patterned by forming a dummy pattern having at least one recess on the unpatterned mask layer, forming a first sidewall spacer structure adjacent to sidewalls of the recess, removing the dummy pattern, forming a second sidewall spacer structure on the first sidewall spacer structure, removing the first sidewall spacer structure, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.

Abstract translation: 本公开提供了形成掩模图案和半导体器件结构的方法，其中可以形成例如约20nm或更小的印刷半间距。 提供一种形成掩模图案的方法，其中在半导体衬底的上表面上设置半导体器件结构上形成未图案化的掩模层，并且对未图案化的掩模层进行图案化以在半导体器件结构上形成掩模图案 。 通过在未图案化的掩模层上形成具有至少一个凹部的虚设图案来形成未图案化的掩模层，形成与凹部的侧壁相邻的第一侧壁间隔结构，去除虚拟图案，在第一侧壁上形成第二侧壁间隔结构 间隔结构，去除第一侧壁间隔结构，以及蚀刻与第二侧壁间隔结构对准的未图案化掩模层。

公开(公告)号：US09111756B2

公开(公告)日：2015-08-18

申请号：US14033789

申请日：2013-09-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joachim Patzer ,  Hans-Peter Moll

IPC: H01L21/44 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/28512 ,  H01L21/76886 ,  H01L27/0629 ,  H01L28/20

Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract translation: 为具有晶体管和电阻器的集成电路提供了方法和装置。 该方法包括在晶体管和电阻器之上沉积第一介电层，随后是非晶硅层。 将非晶硅层注入电阻器上以产生蚀刻掩模，并且在晶体管上去除非晶硅层和第一介电层。 然后将晶体管上的接触位置硅化。

公开(公告)号：US20140248778A1

公开(公告)日：2014-09-04

申请号：US13781874

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hans-Peter Moll ,  Joachim Patzer

IPC: H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66659

Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

Abstract translation: 本文公开的一种示例性方法包括在半导体衬底上形成结构，执行保形沉积工艺以在结构上方形成未掺杂的间隔物材料层，执行成角度的离子注入工艺以在未掺杂的层中形成掺杂间隔物材料的区域 间隔材料，同时留下未掺杂的未掺杂的间隔物材料层的其它部分，并且在执行成角度离子注入工艺之后，执行至少一个蚀刻工艺，其去除未掺杂间隔物材料层的未掺杂部分，从而导致侧壁间隔物 包括位于该结构的至少一侧但不是全部侧面的掺杂间隔物材料。

公开(公告)号：US20190043764A1

公开(公告)日：2019-02-07

申请号：US15667017

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Gunter Grasshoff

IPC: H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

公开(公告)号：US20170317108A1

公开(公告)日：2017-11-02

申请号：US15645686

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L49/02 ,  H01L27/108 ,  H01L27/06 ,  H01L21/84 ,  H01L21/762 ,  H01L21/265 ,  H01L29/94 ,  H01L21/285

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09735174B2

公开(公告)日：2017-08-15

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/265 ,  H01L21/285 ,  H01L21/84 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/786 ,  H01L27/06 ,  H01L29/94

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

公开(公告)号：US20160307926A1

公开(公告)日：2016-10-20

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

Abstract translation: 公开了一种集成电路产品，其包括SOI结构，其包括体半导体衬底，位于体半导体衬底上的掩埋绝缘层和位于绝缘层上的半导体层，其中在SOI结构的第一区域中，半导体层 并且去除了掩埋绝缘层，并且在SOI结构的第二区域中，半导体层和掩埋绝缘层存在于体半导体衬底之上。 该产品还包括半导体本体器件，其包括位于第一区域中的体半导体衬底上的第一栅极结构和包括位于第二区域中的半导体层上的第二栅极结构的SOI半导体器件，其中第一和第二栅极结构 具有基本上延伸到体半导体衬底的上表面上方的共同高度水平的最终栅极高度。

公开(公告)号：US20160204129A1

公开(公告)日：2016-07-14

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H01L27/108 ,  H01L21/265 ,  H01L21/285 ,  H01L29/786 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：提供包括衬底的SOI晶片，在衬底上形成的掩埋氧化物（BOX）层和形成在BOX层上的半导体层，去除半导体 在所述晶片的第一区域中，以暴露所述BOX层，在所述第一区域中的暴露的BOX层上形成介电层，并在所述介电层上形成导电层。 此外，提供了包括形成在晶片上的电容器的半导体器件，其中电容器包括包括晶片的掺杂半导体衬底的第一电容器电极，包括晶片的超薄BOX层的电容器绝缘体和高k 形成在超薄BOX层上的电介质层，以及包含形成在高k电介质层上的导电层的第二电容器电极。

公开(公告)号：US09023709B2

公开(公告)日：2015-05-05

申请号：US14011413

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Marco Lepper ,  Werner Graf

IPC: H01L21/00 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76877

Abstract: When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

Abstract translation: 当形成先进的半导体器件的金属化层时，通常必须用金属（例如铜）填充具有高纵横比的孔。 本公开提供了一种用于在绝缘层中形成具有高纵横比的孔的方便的方法。 该绝缘层可能已经沉积在半导体器件的表面上。 所提出的方法依赖于在绝缘层上执行的离子注入步骤，随后进行蚀刻，其优选为湿蚀刻。