公开(公告)号：US08904335B2

公开(公告)日：2014-12-02

申请号：US13849575

申请日：2013-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hidekazu Yoshida ,  Lei Yuan ,  Paul Mesa

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Evaluation of electrical accessibility within a layer of a circuit to pin geometries residing within a cell boundary of the circuit is provided. The evaluating includes, for instance, checking along substantially parallel pin geometry access paths of the layer to determine possible points at which a respective pin geometry of the pin geometries within the cell boundary may be accessed. The evaluating also includes identifying which points of the possible points are accessible access points by any route of the possible routes for electrically connecting to a respective pin geometry of the pin geometries from a first side or a second side of the cell boundary, wherein at least one point of the possible points is identified as not being an accessible access point based on the at least one point being inaccessible by the possible routes.

Abstract translation: 提供了评估电路层内的电可访问性以引导驻留在电路的单元边界内的几何形状。 评估包括例如沿着层的基本平行的针几何访问路径进行检查，以确定可以访问单元边界内的针几何形状的相应销几何形状的可能点。 评估还包括通过用于电连接到细胞边界的第一侧或第二侧的针几何形状的相应针几何形状的可能路线的任何路线来识别可能点的哪些点是可访问的接入点，其中至少 基于可能的路线不可访问的至少一个点，可能点的一点被识别为不是可访问的接入点。

公开(公告)号：US10559503B2

公开(公告)日：2020-02-11

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/027 ,  H01L27/092 ,  G06F17/50 ,  H01L21/768 ,  H01L27/088

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09905552B1

公开(公告)日：2018-02-27

申请号：US15238107

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Xuelian Zhu ,  Harry J. Levinson

IPC: H01L27/118 ,  H01L27/02 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/11803 ,  H01L27/1211

Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

公开(公告)号：US20180004883A1

公开(公告)日：2018-01-04

申请号：US15200475

申请日：2016-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim

IPC: G06F17/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/528

Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.

公开(公告)号：US09613177B2

公开(公告)日：2017-04-04

申请号：US14578717

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

公开(公告)号：US20160163584A1

公开(公告)日：2016-06-09

申请号：US14674792

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jia Zeng ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/027 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract translation: 一种方法包括在硬掩模层之上形成心轴元件，在心轴元件上形成第一和第二间隔物，去除心轴元件，限定在第一和第二间隔物之间​​的第一开口，并暴露硬掩模层的一部分并具有 沿第一方向延伸的纵轴，形成覆盖所述第一开口的中间部分的阻挡掩模，所述阻挡掩模具有在与所述第一方向不同的第二方向上延伸的纵向轴线;在所述阻挡掩模的存在下， 阻挡掩模和所述第一和第二间隔物，以限定在所述硬掩模层中沿所述第一方向延伸的对准的第一和第二线段开口，基于所述第一和第二线段开口蚀刻设置在所述硬掩模层下方的电介质层中的凹陷， 并用导电材料填充凹部。

公开(公告)号：US09330221B2

公开(公告)日：2016-05-03

申请号：US14286395

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules.

Abstract translation: 公开了基于掩模设计规则和所得到的设备来布线金属路由层的方法。 实施例可以包括在半导体设计布局中布置连续金属线，以及根据切割或块掩模设计规则，根据切割或块掩模的放置，利用处理器路由使用连续金属线的金属布线层。

公开(公告)号：US09158879B2

公开(公告)日：2015-10-13

申请号：US14017594

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Soo Han Choi ,  Li Yang ,  Jongwook Kye

IPC: G06F17/30 ,  G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

Abstract translation: 公开了在IC设计中能够产生颜色不可确定的多边形的方法和装置。 实施例包括：确定在IC设计中水平延伸的多个第一路线，所述多条第一路线中的​​每条路线被放置在所述IC设计的多个相等间隔的垂直位置之一上; 确定第二路线是否与所述多个等间隔垂直位置的垂直位置之一重叠; 以及基于所述第二路由是否重叠的确定来选择所述第二路由的设计规则。

公开(公告)号：US09041087B2

公开(公告)日：2015-05-26

申请号：US14288034

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jin Cho ,  Jongwook Kye

IPC: H01L29/66 ,  H01L23/48 ,  H01L21/4763 ,  H01L29/423 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L21/76834 ,  H01L21/76888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.

Abstract translation: 提供半导体器件结构。 示例性的半导体器件结构包括半导体材料的衬底和覆盖衬底的栅极结构。 半导体衬底还包括形成在靠近栅极结构的衬底中的掺杂区域和覆盖掺杂区域的第一电介质材料。 半导体衬底还包括形成在第一电介质材料中的导电触点，导电触点电连接到掺杂区域，以及覆盖在导电触点上的电介质盖。

公开(公告)号：US09035679B2

公开(公告)日：2015-05-19

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。