公开(公告)号：US10770407B2

公开(公告)日：2020-09-08

申请号：US16240436

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhuojie Wu ,  Cathryn J. Christiansen ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald G. Filippi, Jr. ,  Eric D. Hunt-Schroeder ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  H01L23/538 ,  G01N27/12

Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

公开(公告)号：US20200219826A1

公开(公告)日：2020-07-09

申请号：US16240436

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhuojie Wu ,  Cathryn J. Christiansen ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald G. Filippi, JR. ,  Eric D. Hunt-Schroeder ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  G01N27/12 ,  H01L23/538

Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

公开(公告)号：US10438902B2

公开(公告)日：2019-10-08

申请号：US15698027

申请日：2017-09-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vincent J. McGahay ,  Nicholas A. Polomoff ,  Shaoning Yao ,  Anupam Arora

IPC: H01L23/00 ,  H01L23/62 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.

公开(公告)号：US20180315707A1

公开(公告)日：2018-11-01

申请号：US15498083

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/562

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US09343420B2

公开(公告)日：2016-05-17

申请号：US14181616

申请日：2014-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brian M. Erwin ,  Eric D. Perfecto ,  Nicholas A. Polomoff ,  Jae-Woong Nah

IPC: H01L23/16 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13147 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27515 ,  H01L2224/27632 ,  H01L2224/2784 ,  H01L2224/29023 ,  H01L2224/29028 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/32147 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83885 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/0665 ,  H01L2224/81805 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/27

Abstract: Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.

Abstract translation: 制造包括嵌入在预填充材料和/或阻焊剂的预涂层中的焊料凸块的电子器件，从而提高芯片封装相互作用的可靠性。 底部填充物可以直接施加到晶片上，从而增加填料的填充量。 在底部填充和/或阻焊涂层中形成的通道暴露导电垫或金属柱。 可以用熔融焊料填充这样的通道以形成焊料凸块。