公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20160086849A1

公开(公告)日：2016-03-24

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L21/768

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US10381442B2

公开(公告)日：2019-08-13

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180240875A1

公开(公告)日：2018-08-23

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US09972682B2

公开(公告)日：2018-05-15

申请号：US15004756

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20170301697A1

公开(公告)日：2017-10-19

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02623 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/01 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7848

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

公开(公告)号：US09335759B2

公开(公告)日：2016-05-10

申请号：US14177260

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas L. Breil ,  Oleg Gluschenkov ,  Keith Kwong Hon Wong

IPC: G06F17/50 ,  G05B19/418

CPC classification number: G05B19/41865 ,  G05B2219/32301 ,  G05B2219/45032 ,  H01L21/268 ,  H01L21/324 ,  H01L22/14 ,  H01L22/20 ,  Y02P90/02 ,  Y02P90/20 ,  Y02P90/26

Abstract: Semiconductor chips with curable out of specification measured values of an anneal-activated parameter are identified at a test step. A plurality of anneal plans are generated to include at least one of the identified semiconductor chips. A net yield improvement is calculated for each anneal plan. Each anneal plan includes the paths of a laser beam across the wafer to be irradiated, and optionally includes an azimuthal angle of the wafer as a function of time. The net yield improvement is the difference between an estimated yield improvement from selected target semiconductor chips for irradiation and an estimated yield loss due to collateral irradiation of functional semiconductor chips for each anneal plan. After simulating the net yield improvements for all the anneal plans, the anneal plan providing the greatest net yield improvement can be selected and utilized.

Abstract translation: 在测试步骤中识别具有退火激活参数的规格测量值的可固化的半导体芯片。 生成多个退火计划以包括所识别的半导体芯片中的至少一个。 对每个退火计划计算净产量改进。 每个退火计划包括穿过要照射的晶片的激光束的路径，并且可选地包括作为时间的函数的晶片的方位角。 净收益率的改善是所选择的用于照射的目标半导体芯片的估计产量提高与由于每个退火计划的功能性半导体芯片的侧向照射而导致的估计的产量损失之间的差异。 在模拟所有退火计划的净产量改进之后，可以选择和利用提供最大净产量改进的退火计划。

公开(公告)号：US10068920B2

公开(公告)日：2018-09-04

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/324

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.