-
公开(公告)号：US10586855B2
公开(公告)日：2020-03-10
申请号：US15961264
申请日：2018-04-24
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L29/51 , H01L27/092 , H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/84 , H01L21/8238 , H01L21/02 , H01L21/28 , H01L27/12
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
-
公开(公告)号：US20190027370A1
公开(公告)日：2019-01-24
申请号：US15653594
申请日：2017-07-19
Applicant: GLOBALFOUNDRIES Inc.
Inventor： George R. Mulfinger , Hyun-Jin Cho , Anil Kumar , Timothy J. McArdle
IPC: H01L21/306 , H01L29/08 , H01L21/02 , H01L29/06 , H01L29/66
Abstract: Methods of forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.
-
公开(公告)号：US09666791B2
公开(公告)日：2017-05-30
申请号：US14841997
申请日：2015-09-01
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Xunyuan Zhang , Ruilong Xie , Xiuyu Cai , Seowoo Nam , Hyun-Jin Cho
CPC classification number: H01L43/08 , G11C11/161 , H01L21/02 , H01L27/222 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/12
Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.
-
公开(公告)号：US20160365450A1
公开(公告)日：2016-12-15
申请号：US15208121
申请日：2016-07-12
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L29/78 , H01L29/66 , H01L21/02 , H01L21/8238 , H01L29/49 , H01L29/423 , H01L27/092
CPC classification number: H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
-
公开(公告)号：US20160365346A1
公开(公告)日：2016-12-15
申请号：US14735984
申请日：2015-06-10
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/66
CPC classification number: H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。
-
Patent Agency Ranking
16.发明申请METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A SPACER ETCH BLOCK CAP AND THE RESULTING DEVICE 有权形成具有间隔隔离块和半导体器件的半导体器件的方法公开(公告)号：US20150318178A1
公开(公告)日：2015-11-05
申请号：US14268579
申请日：2014-05-02
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Daniel T. Pham , Hyun-Jin Cho , Ruilong Xie
IPC: H01L21/28 , H01L29/423 , H01L29/417 , H01L21/283
CPC classification number: H01L21/28 , H01L21/28247 , H01L21/283 , H01L21/76897 , H01L29/417 , H01L29/41775 , H01L29/423 , H01L29/42364 , H01L29/66545
Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.
Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成侧壁隔离物，去除牺牲栅极结构并在其位置形成替代栅极结构 在形成替代栅极结构之后的某些点，执行蚀刻工艺以降低间隔物的高度，从而限定具有部分限定间隔物凹槽的上表面的凹进的间隔件，并且在上表面上形成间隔物蚀刻块帽 每个凹进的间隔结构和间隔凹槽内。
-
公开(公告)号：US20180240884A1
公开(公告)日：2018-08-23
申请号：US15961264
申请日：2018-04-24
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L29/51 , H01L29/78 , H01L27/12 , H01L29/66 , H01L27/092 , H01L29/423 , H01L21/8238 , H01L29/49 , H01L21/02 , H01L21/28
CPC classification number: H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
-
公开(公告)号：US10002940B2
公开(公告)日：2018-06-19
申请号：US15363563
申请日：2016-11-29
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L29/51 , H01L27/092 , H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/8238 , H01L21/02 , H01L21/28 , H01L27/12
CPC classification number: H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
-
公开(公告)号：US09646969B2
公开(公告)日：2017-05-09
申请号：US15208121
申请日：2016-07-12
Inventor： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/8238 , H01L21/02 , H01L21/28
CPC classification number: H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
-
20.发明授权Methods of forming a semiconductor device with a spacer etch block cap and the resulting device 有权用间隔物蚀刻块帽形成半导体器件的方法和所得到的器件公开(公告)号：US09466491B2
公开(公告)日：2016-10-11
申请号：US14268579
申请日：2014-05-02
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Daniel T. Pham , Hyun-Jin Cho , Ruilong Xie
IPC: H01L21/28 , H01L21/283 , H01L29/423 , H01L29/417 , H01L21/768
CPC classification number: H01L21/28 , H01L21/28247 , H01L21/283 , H01L21/76897 , H01L29/417 , H01L29/41775 , H01L29/423 , H01L29/42364 , H01L29/66545
Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.
Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成侧壁隔离物，去除牺牲栅极结构并在其位置形成替代栅极结构 在形成替代栅极结构之后的某些点，执行蚀刻工艺以降低间隔物的高度，从而限定具有部分限定间隔物凹槽的上表面的凹进的间隔件，并且在上表面上形成间隔物蚀刻块帽 每个凹进的间隔结构和间隔凹槽内。
-
-
-
-
-
-
-
-
-
Search Results
30
records
(took 0.02 seconds)
