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    Using trap routines in a RISC microprocessor architecture
    13.
    发明申请
    Using trap routines in a RISC microprocessor architecture 审中-公开
    在RISC微处理器架构中使用陷阱程序

    公开(公告)号：US20080071991A1

    公开(公告)日：2008-03-20

    申请号：US11981482

    申请日：2007-10-31

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

    摘要翻译： 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元（CPU）指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 微处理单元（MPU）包含52个通用寄存器，包括16个全局数据寄存器，一个索引寄存器，一个计数寄存器，一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器，缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。 此外，MPU还包含一个模式/状态寄存器和41个用于I / O，控制，配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据，计数事件，测量时间和执行其他与时序相关的功能的输入输出处理器（IOP）。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行，允许MPU和IOP在单个时钟周期内发出和完成指令，每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时，CPU使用8位操作码，最多可从内存中获取四条指令。 这些指令可以重复，而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时，这将保持高性能。

    Flow of streaming data through multiple processing modules
    14.
    发明申请
    Flow of streaming data through multiple processing modules 有权
    流数据流通过多个处理模块

    公开(公告)号：US20050267988A1

    公开(公告)日：2005-12-01

    申请号：US11195092

    申请日：2005-08-02

    申请人： Rafael Lisitsa ,  George Shaw ,  Dale Sather ,  Bryan Woodruff

    发明人： Rafael Lisitsa ,  George Shaw ,  Dale Sather ,  Bryan Woodruff

    IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/54 ,  G06F8/45 ,  G06F9/546

    摘要： Frame-based streaming data flows through a graph of multiple interconnected processing modules. The modules have a set of performance parameters whose values specify the sensitivity of each module to the selection of certain resources of a system. A user specifies overall goals for an actual graph for processing a given type of data for a particular purpose. A flow manager constructs the graph as a sequence of module interconnections required for processing the data, in response to the parameter values of the individual modules in the graph in view of the goals for the overall graph as a whole, and divides it into pipes each having one or more modules and each assigned to a memory manager for handling data frames in the pipe.

    摘要翻译： 基于帧的流数据流经过多个互连处理模块的图形。 这些模块具有一组性能参数，其值指定每个模块对系统某些资源的选择的灵敏度。 用户为特定目的指定用于处理给定类型的数据的实际图形的总体目标。 考虑到整个图形的目标，流程管理器响应于图中各个模块的参数值，将图形构建为处理数据所需的模块互连序列，并将其划分为管道 具有一个或多个模块，并且每个模块被分配给用于处理管道中的数据帧的存储器管理器。

    Resource manager architecture
    15.
    发明申请
    Resource manager architecture 有权
    资源管理器架构

    公开(公告)号：US20050044205A1

    公开(公告)日：2005-02-24

    申请号：US10931058

    申请日：2004-08-31

    申请人： Mukund Sankaranarayan ,  Forrest Foltz ,  George Shaw ,  Dale Sather ,  Andy Raffman ,  Jai Srinivasan ,  Terje Backman ,  William Parry ,  David Bakin ,  Michael Jones ,  Sean McDowell ,  Jayachandran Raja ,  Robin Speed

    发明人： Mukund Sankaranarayan ,  Forrest Foltz ,  George Shaw ,  Dale Sather ,  Andy Raffman ,  Jai Srinivasan ,  Terje Backman ,  William Parry ,  David Bakin ,  Michael Jones ,  Sean McDowell ,  Jayachandran Raja ,  Robin Speed

    IPC分类号： G06F9/52 ,  G06F9/46 ,  G06F9/50 ,  G06F15/173

    CPC分类号： G06F9/50 ,  G06F9/526 ,  G06F2209/5014 ,  G06F2209/522 ,  H04N21/4424 ,  H04N21/443

    摘要： Resource management architectures implemented in computer systems to manage resources are described. In one embodiment, a general architecture includes a resource manager and multiple resource providers that support one or more resource consumers such as a system component or application. Each provider is associated with a resource and acts as the manager for the resource when interfacing with the resource manager. The resource manager arbitrates access to the resources provided by the resource providers on behalf of the consumers. A policy manager sets various policies that are used by the resource manager to allocate resources. One policy is a priority-based policy that distinguishes among which applications and/or users have priority over others to use the resources. A resource consumer creates an “activity” at the resource manager and builds one or more “configurations” that describe various sets of preferred resources required to perform the activity. Each resource consumer can specify one or more configurations for each activity. If multiple configurations are specified, the resource consumer can rank them according to preference. This allows the resource consumers to be dynamically changed from one configuration to another as operating conditions change.

    摘要翻译： 描述了在计算机系统中实现的管理资源的资源管理架构。 在一个实施例中，一般架构包括资源管理器和支持一个或多个资源消费者（诸如系统组件或应用程序）的多个资源提供者。 当与资源管理器进行接口时，每个提供者都与资源相关联并充当该资源的管理器。 资源管理员代表消费者对资源提供者提供的资源的访问进行仲裁。 策略管理器设置资源管理器使用的各种策略来分配资源。 一个策略是一个基于优先级的策略，区分哪些应用程序和/或用户优先于其他应用程序和/或用户来使用资源。 资源消费者在资源管理器中创建“活动”，并构建一个或多个描述执行活动所需的各种首选资源集的“配置”。 每个资源消费者可以为每个活动指定一个或多个配置。 如果指定了多个配置，资源消费者可以根据偏好对其进行排名。 这允许在操作条件改变时资源消费者从一个配置动态地改变另一个配置。

    Abrasive and polishing sheets
    16.
    发明授权
    Abrasive and polishing sheets 失效
    磨料和抛光片

    公开(公告)号：US4437269A

    公开(公告)日：1984-03-20

    申请号：US175586

    申请日：1980-08-05

    申请人： George Shaw

    发明人： George Shaw

    IPC分类号： A44B18/00 ,  B24D11/00 ,  B24D11/02

    CPC分类号： A44B18/00 ,  B24D11/00

    摘要： An abrasive or polishing sheet has indicia carried on its rear face overlaid by a translucent textile material providing a surface engageable by hooks, the material being adhered to the said indicia and their information content remain discernible through the said material. The sheet can be secured to a hooked surface of a carrier unit and can be removed therefrom and reused. The grit size indication is provided without needing to print the fabric.The textile material is a brushed, knitted nylon having less than 20 loops or curls per square mm. A carrier pad has a material to which the sheet can be attached. The material of the pad has inclined stalks extending therefrom which have unhooked ends. These features result in a very low peel strength between sheet and pad.

    摘要翻译： 研磨片或抛光片的后表面上带有标示，该标记覆盖着半透明的纺织材料，其提供可通过钩接合的表面，该材料被粘附到所述标记上，并且其信息内容可以通过所述材料辨别。 片材可以固定到承载单元的钩形表面上，并且可以将其移除并重复使用。 提供砂粒尺寸指示，无需打印织物。 纺织材料是具有小于20圈或每平方毫米卷发的拉丝针织尼龙。 载体垫具有可附着片材的材料。 垫的材料具有从其延伸的倾斜茎具有未钩端。 这些特征导致片材和垫片之间的剥离强度非常低。

    Interactive video system
    17.
    发明授权
    Interactive video system 有权
    互动视频系统

    公开(公告)号：US08910208B2

    公开(公告)日：2014-12-09

    申请号：US12962529

    申请日：2010-12-07

    申请人： Anthony Hartman ,  George Shaw

    发明人： Anthony Hartman ,  George Shaw

    IPC分类号： H04N7/14 ,  H04N5/445 ,  H04N7/173 ,  H04N21/475 ,  H04N7/15 ,  H04N21/4788 ,  H04N21/422 ,  H04N21/4223 ,  H04N21/443

    CPC分类号： H04N21/4788 ,  H04N7/15 ,  H04N21/42203 ,  H04N21/4223 ,  H04N21/4438 ,  H04N21/4755

    摘要： An interactive video system is provided that is capable of combining streaming televised events with video conferencing technology to create a social television experience. A first user is able to connect via a webcam and microphone to a server that combines the webcam video and sound from the microphone with a streaming video that could be a televised event. The combined webcam video, microphone sound, and streaming video is then broadcast to the first user and other users such that the users are capable of viewing the streaming video with the live conferencing video and sound from the first user. This procedure may be repeated such that a plurality of users may video conference live on top of the streaming video.

    摘要翻译： 提供了一种交互式视频系统，其能够将流媒体电视事件与视频会议技术相结合，以创建社交电视体验。 第一个用户能够通过网络摄像头和麦克风连接到将麦克风的网络摄像头视频和声音与可以是电视转播事件的流式视频相结合的服务器。 然后将组合的网络摄像头视频，麦克风声音和流视频广播到第一用户和其他用户，使得用户能够使用来自第一用户的现场会议视频和声音来观看流式视频。 可以重复该过程，使得多个用户可以在流式视频的顶部上进行视频会议。

    APPARATUSES AND METHODS FOR NEUROLOGICAL STATUS EVALUATION USING ELECTROMAGNETIC SIGNALS
    18.
    发明申请
    APPARATUSES AND METHODS FOR NEUROLOGICAL STATUS EVALUATION USING ELECTROMAGNETIC SIGNALS 有权
    使用电磁信号进行神经病学状态评估的装置和方法

    公开(公告)号：US20140243647A1

    公开(公告)日：2014-08-28

    申请号：US13977689

    申请日：2011-12-30

    申请人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    发明人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    IPC分类号： A61B5/00 ,  A61B5/02

    CPC分类号： A61B5/04008 ,  A61B5/0042 ,  A61B5/0075 ,  A61B5/02042 ,  A61B5/04001 ,  A61B5/4064 ,  A61B5/4094 ,  A61B5/4878 ,  A61B5/6803 ,  A61B5/7225 ,  A61B5/7257 ,  A61B5/7282 ,  A61B5/742 ,  A61B5/746 ,  A61B2562/0223 ,  A61B2576/026

    摘要： In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.

    摘要翻译： 在一个实施例中，神经状态评估装置包括被配置为产生一个或多个频率的电磁信号的信号发生器，耦合到信号发生器并被配置为传送电磁信号的发射天线以及靠近发射 天线，使得在发射天线和接收天线之间定义评估空间。 所评估的生物组织不接触发射天线或接收天线。 接收天线在评估后通过生物组织传播后接收调制电磁信号。 神经状态评估装置还包括耦合到接收天线的频谱分析仪，其中频谱分析仪接收并采样调制的电磁信号。 计算设备耦合到频谱分析仪，计算评估，并根据评估参数提供正在评估的生物组织的神经状态指标。

    Transferring data between registers in a RISC microprocessor architecture
    20.
    发明申请
    Transferring data between registers in a RISC microprocessor architecture 审中-公开

    公开(公告)号：US20080091920A1

    公开(公告)日：2008-04-17

    申请号：US11981237

    申请日：2007-10-31

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F9/00 ,  G06F9/30

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.