公开(公告)号：US10784143B2

公开(公告)日：2020-09-22

申请号：US16263650

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang ,  Yue Zhong

IPC: H01L29/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/3213 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

公开(公告)号：US10777642B2

公开(公告)日：2020-09-15

申请号：US16262105

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

公开(公告)号：US10777637B2

公开(公告)日：2020-09-15

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US10763176B2

公开(公告)日：2020-09-01

申请号：US16668500

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.

公开(公告)号：US20200227404A1

公开(公告)日：2020-07-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/522

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

公开(公告)号：US20200176587A1

公开(公告)日：2020-06-04

申请号：US16777243

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Hui Zang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.

公开(公告)号：US20200126863A1

公开(公告)日：2020-04-23

申请号：US16668500

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.

公开(公告)号：US10586736B2

公开(公告)日：2020-03-10

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Ruilong Xie ,  Shesh Mani Pandey ,  Hui Zang ,  Garo Jacques Derderian ,  Scott Beasor

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US10475693B1

公开(公告)日：2019-11-12

申请号：US16002403

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.

公开(公告)号：US10468481B2

公开(公告)日：2019-11-05

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Chun Yu Wong ,  Kwan-Yong Lim

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.