公开(公告)号：US20210066474A1

公开(公告)日：2021-03-04

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US10727327B2

公开(公告)日：2020-07-28

申请号：US15882053

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul Mishra ,  Vibhor Jain ,  Ajay Raman ,  Robert J. Gauthier

IPC: H01L29/749 ,  H01L29/66 ,  H01L29/74 ,  H01L27/02 ,  H01L29/737

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

公开(公告)号：US10446644B2

公开(公告)日：2019-10-15

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/732

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

公开(公告)号：US20190273028A1

公开(公告)日：2019-09-05

申请号：US15910603

申请日：2018-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

Abstract: Structures and methods associated with a silicon-on-insulator substrate are needed. A silicon-on-insulator substrate is provided that includes a device layer of single-crystal semiconductor material, a buried oxide layer, a handle wafer of single-crystal semiconductor material, and a non-single-crystal semiconductor layer between the handle wafer and the buried oxide layer. A trench is formed that extends through the device layer, the buried oxide layer, and the non-single-crystal semiconductor layer to the handle wafer. A semiconductor layer is epitaxially grown from the handle wafer to at least partially fill the trench, and a device structure is formed using at least a portion of the semiconductor layer.

公开(公告)号：US10312356B1

公开(公告)日：2019-06-04

申请号：US16013363

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  Sarah McTaggart ,  Mark Levy

IPC: H01L31/0328 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/265

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.

公开(公告)号：US20190067905A1

公开(公告)日：2019-02-28

申请号：US15692136

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Ellis-Monaghan ,  Sebastian Ventrone ,  Vibhor Jain ,  Yves Ngu

IPC: H01S5/062 ,  H01S5/00 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S5/223 ,  H01S5/22

Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

公开(公告)号：US10211090B2

公开(公告)日：2019-02-19

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L23/482 ,  H01L23/31

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US10121884B2

公开(公告)日：2018-11-06

申请号：US15806532

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/8249 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/737 ,  H01L29/66 ,  H01L21/8226 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L29/732 ,  H03F3/213

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

公开(公告)号：US20180286968A1

公开(公告)日：2018-10-04

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

CPC classification number: H01L29/732 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US10014397B1

公开(公告)日：2018-07-03

申请号：US15383171

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.