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公开(公告)号：US20090170262A1
公开(公告)日：2009-07-02
申请号：US12397905
申请日：2009-03-04
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926 , Y10S438/962
摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.
摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。
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公开(公告)号：US06887758B2
公开(公告)日：2005-05-03
申请号：US10267153
申请日：2002-10-09
IPC分类号： H01L21/336 , H01L29/792 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.
摘要翻译： 半导体器件（10）具有均匀地注入到半导体衬底（20）中的具有第一导电类型的高掺杂层（26）。 氧化物 - 氧化物 - 氧化物结构（36,38,40）形成在半导体衬底（20）上。 具有第一导电类型的卤素区域（46）以仅在氧化物 - 氧化物 - 氧化物结构的漏极侧的角度被注入，并且在氧化物 - 氮化物 - 氧化物结构之下延伸到氧化氮化物 - 氮化物的边缘的预定距离 氧化物结构。 具有第二导电类型的源极（52）和漏极（54）被注入衬底（20）中。 所得的非易失性存储单元提供低的自然阈值电压，以在读周期期间最小化阈值电压漂移。 此外，在漏极侧使用卤素区域（46）允许更高的编程速度，并且高掺杂层（26）允许使用短通道器件。
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13.发明授权Back-gated semiconductor device with a storage layer and methods for forming thereof 有权具有存储层的后门控半导体器件及其形成方法公开(公告)号：US07679125B2
公开(公告)日：2010-03-16
申请号：US11300077
申请日：2005-12-14
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译： 制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。 存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。 该方法还包括将第二晶片的第一侧布置到第一晶片。 该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。 该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。
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14.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07094645B2
公开(公告)日：2006-08-22
申请号：US10944239
申请日：2004-09-17
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个相邻的浮置栅极层。 顶层制成具有轮廓，同时使下层基本上保持不变。 一个层间电介质和一个控制栅极跟随着浮栅的轮廓，以增加控制栅和浮栅之间的电容。 浮栅的两层可以是多晶硅，其中顶层具有通过使用牺牲层形成在其中的轮廓。 牺牲层形成在底部多晶硅层上并被蚀刻。 顶部多晶硅层形成在牺牲层上。 顶部多晶硅层的后续处理暴露了牺牲层的剩余部分，使得其可以被去除; 将轮廓留在层间电介质和控制栅极的顶部多晶硅层中。
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公开(公告)号：US07544980B2
公开(公告)日：2009-06-09
申请号：US11342155
申请日：2006-01-27
IPC分类号： H01L29/06
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0466 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/785 , H01L29/792
摘要： A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.
摘要翻译： 使用半导体鳍片实现存储器单元，其中沟道区域沿着源极和漏极区域之间的鳍片的侧壁。 通道区域的一部分具有与其相邻的选择栅极，而另一部分具有与其相邻的控制栅极，其间具有电荷存储结构。 在一些实施例中，独立的控制栅极结构位于鳍的相对侧壁附近，以便实现两个存储单元。
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公开(公告)号：US07195983B2
公开(公告)日：2007-03-27
申请号：US10930892
申请日：2004-08-31
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。
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公开(公告)号：US06964902B2
公开(公告)日：2005-11-15
申请号：US10787510
申请日：2004-02-26
申请人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
发明人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
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公开(公告)号：US07391659B2
公开(公告)日：2008-06-24
申请号：US11341809
申请日：2006-01-27
IPC分类号： G11C29/00
CPC分类号： G11C16/0466 , G11C16/12 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.
摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。
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公开(公告)号：US07317222B2
公开(公告)日：2008-01-08
申请号：US11341813
申请日：2006-01-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/66833
摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.
摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。
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公开(公告)号：US07105395B2
公开(公告)日：2006-09-12
申请号：US10930891
申请日：2004-08-31
IPC分类号： H01L29/72
CPC分类号： H01L29/0847 , H01L29/7881 , H01L29/7885
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.
摘要翻译： 非易失性存储器（NVM）具有朝向衬底表面逐渐更加掺杂的硅锗（SiGe）漏极。 衬底优选为硅，并且通过首先在漏极位置中的衬底中形成空腔来形成漏极。 SiGe在掺杂水平增加的情况下外延生长。 因此，衬底和漏极之间的PN结在P和N侧都被轻掺杂。 漏极逐渐变得更加重掺杂，直到达到最大期望的掺杂水平，并且SiGe漏极的剩余部分以该最大期望水平掺杂。 作为进一步的增强，衬底中SiGe的周长与衬底和沟道的导电类型相同。 因此，通道的一部分在SiGe中。
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