公开(公告)号：US09837147B2

公开(公告)日：2017-12-05

申请号：US15307486

申请日：2014-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  Adam L. Ghozeil ,  Brent Buchanan

IPC: G11C13/00 ,  G11C27/02

CPC classification number: G11C13/0038 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0092

Abstract: A device for regulating memristor switching pulses is described. The device includes a voltage source to supply a voltage to a memristor. The device also includes a voltage detector to detect a memristor voltage. The memristor voltage is based on an initial resistance state of the memristor and the voltage supplied by the voltage source. The device also includes a comparator to compare the memristor voltage with a target voltage value for the memristor. The device also includes a feedback loop to indicate to a control switch when the memristor voltage is at least equal to the target voltage value. The device also includes a control switch to cut off the memristor from the voltage source when the memristor voltage is at least equal to the target voltage value.

公开(公告)号：US20170213591A1

公开(公告)日：2017-07-27

申请号：US15329776

申请日：2014-09-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Yoocharn Jeon

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/77

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.

公开(公告)号：US20170148513A1

公开(公告)日：2017-05-25

申请号：US15116105

申请日：2014-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0021 ,  G11C13/0007 ,  G11C27/00 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H03G1/0088

Abstract: Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.

公开(公告)号：US11232352B2

公开(公告)日：2022-01-25

申请号：US16037060

申请日：2018-07-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

公开(公告)号：US20210193222A1

公开(公告)日：2021-06-24

申请号：US16065364

申请日：2016-01-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Emmanuelle J. Merced Grafals ,  Brent Buchanan ,  Le Zheng

IPC: G11C13/00

Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

公开(公告)号：US10418103B1

公开(公告)日：2019-09-17

申请号：US15958903

申请日：2018-04-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng ,  Catherine Graves

IPC: G11C15/00 ,  G11C15/04 ,  G11C13/00 ,  G11C7/06

Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

公开(公告)号：US10332592B2

公开(公告)日：2019-06-25

申请号：US15570951

申请日：2016-03-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Brent Buchanan ,  Le Zheng

IPC: G11C11/54 ,  G06F9/06 ,  G06N3/063 ,  G11C13/00 ,  G11C7/10 ,  G06N3/04

Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

公开(公告)号：US10242736B2

公开(公告)日：2019-03-26

申请号：US15318718

申请日：2014-07-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C16/06 ,  G11C13/00 ,  G11C7/06 ,  G11C11/56 ,  G11C7/14

Abstract: An example device includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current, and provide a first output. The second module is to compare the input current to a second reference current, and provide a second output. The third module is to compare the first output to the second output, and provide a third output indicative of a state associated with the input current.

公开(公告)号：US20180374520A1

公开(公告)日：2018-12-27

申请号：US16117509

申请日：2018-08-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar ,  Brent Buchanan

IPC: G11C7/22 ,  H03M1/66 ,  H03M1/34 ,  H03K21/02

CPC classification number: G11C7/22 ,  G11C7/16 ,  H03K21/02 ,  H03M1/1215 ,  H03M1/34 ,  H03M1/38 ,  H03M1/56 ,  H03M1/66

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

公开(公告)号：US10037804B1

公开(公告)日：2018-07-31

申请号：US15418040

申请日：2017-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C11/00 ,  G11C13/00 ,  G06F17/16

Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.