公开(公告)号：US11370223B2

公开(公告)日：2022-06-28

申请号：US16951234

申请日：2020-11-18

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Noorashekin Binte Jamil

IPC: B41J2/17 ,  B41J2/175 ,  G11C16/06

Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.

公开(公告)号：US11292263B2

公开(公告)日：2022-04-05

申请号：US16316287

申请日：2016-09-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Michael W. Cumbie ,  Yee Kiat Ng

IPC: B41J2/175

Abstract: Aspects relating to an ink container for an image reproduction device are described herein. The ink container includes a body and an electrical connection. The body is formed by molding a polymer material having a metal seed layer. The electrical connection is formed by metallizing a plurality of traces in the metal seed layer. The electrical connection extends from an inside wall of the ink container to an outer wall. A width of the electrical connection on the inside wall of the ink container gradually varies from a bottom of the ink container to a rim.

公开(公告)号：US20220063262A1

公开(公告)日：2022-03-03

申请号：US17454069

申请日：2021-11-09

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

公开(公告)号：US20210221144A1

公开(公告)日：2021-07-22

申请号：US17223239

申请日：2021-04-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Noorashekin Binte Jamil

IPC: B41J2/175 ,  B41J2/045 ,  G11C5/02 ,  G11C16/08 ,  G11C16/24

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

公开(公告)号：US10913265B2

公开(公告)日：2021-02-09

申请号：US16607441

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a system includes a plurality of fluid ejection devices, a fluid ejection controller, and a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices. A first data line of the plurality of data lines communicates data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and a second data line of the plurality of data lines communicates data of a second memory of the first fluid ejection device.

公开(公告)号：US20190381802A1

公开(公告)日：2019-12-19

申请号：US16480127

申请日：2017-01-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Noorashekin Binte Jamil

IPC: B41J2/175 ,  G11C16/08 ,  G11C16/24 ,  G11C5/02 ,  B41J2/045

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

公开(公告)号：US10449776B2

公开(公告)日：2019-10-22

申请号：US16125701

申请日：2018-09-08

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Alexander Govyadinov ,  Adam L. Ghozeil ,  Boon Bing Ng ,  Patrick Leonard ,  Raymond Connolly

IPC: B41J2/175 ,  B41J2/045 ,  B41J2/14 ,  B41J2/18

Abstract: A print head has a fluid slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A circulation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the circulation passage.

公开(公告)号：US10099484B2

公开(公告)日：2018-10-16

申请号：US15520338

申请日：2014-10-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Alexander Govyadinov ,  Adam L Ghozeil ,  Boon Bing Ng ,  Patrick Leonard ,  Raymond Connolly

IPC: B41J2/175 ,  B41J2/18

Abstract: A print head has an ink slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A recirculation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the recirculation passage.

公开(公告)号：US09928912B2

公开(公告)日：2018-03-27

申请号：US15489272

申请日：2017-04-17

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: G11C11/34 ,  G11C16/08 ,  G11C8/04 ,  G11C16/24 ,  G11C8/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11514 ,  H01L29/423 ,  H01L29/78 ,  G11C8/12 ,  H01L27/11582

CPC classification number: G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US20170210124A1

公开(公告)日：2017-07-27

申请号：US15327774

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: B41J2/045

CPC classification number: B41J2/0455 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2/04581

Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing ceil, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.