公开(公告)号：US07834407B2

公开(公告)日：2010-11-16

申请号：US12471680

申请日：2009-05-26

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L27/088

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。

公开(公告)号：US20060261391A1

公开(公告)日：2006-11-23

申请号：US11432491

申请日：2006-05-12

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L29/94

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成保护二极管的功率MISFET的源极区域和n + H +型半导体区域。

公开(公告)号：US20050032287A1

公开(公告)日：2005-02-10

申请号：US10885319

申请日：2004-07-07

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L21/822 ,  H01L21/265 ,  H01L21/336 ,  H01L27/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L29/94 ,  H01L31/0328

CPC分类号： H01L29/7813 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727

摘要： A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n−-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n−-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n−-type single crystal silicon layer.

摘要翻译： 一种半导体器件，其中在不增加电池间距的情况下改善功率MISFET的雪崩承受能力。 在半导体器件中，具有p型导电的杂质离子，例如， B离子从接触孔的底部引入以形成p型半导体区域，其设置在p +型半导体区域下方并与p +型半导体区域接触，并且n < >型单晶硅层，其杂质浓度低于p +型半导体区域。 在p型半导体区域的下方设置的与p型半导体区域接触的n型单晶硅层中形成n型半导体区域，其杂质浓度比n < >型单晶硅层。

公开(公告)号：US20050167746A1

公开(公告)日：2005-08-04

申请号：US11097295

申请日：2005-04-04

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/15

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p− type semiconductor region and p− type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n− type single crystal silicon layer 1B is ρ (Ω·cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.14892 .

摘要翻译： 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个栅极线区域中同时形成p +型半导体区域和p-O +型场限制环 杂质离子注入步骤使其与形成有栅极引出电极的沟槽接触。 在形成时，假设设置在沟槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则CHSP为 设定为满足以下等式：CHSP <= 3.80 + 0.148 92。

公开(公告)号：US08741699B2

公开(公告)日：2014-06-03

申请号：US13479360

申请日：2012-05-24

申请人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

发明人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

IPC分类号： H01L21/332

CPC分类号： H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

摘要： Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

摘要翻译： 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

公开(公告)号：US20070045727A1

公开(公告)日：2007-03-01

申请号：US11508860

申请日：2006-08-24

申请人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi

发明人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/66712 ,  H01L29/7806

摘要： A technology capable of realizing a MOSFET with low ON-resistance and low feedback capacitance, in which the punch through of a channel layer can be prevented even when the shallow junction of the channel layer is formed in a planar type MOSFET is provided. A P type polysilicon is used for a gate electrode in a planar type MOSFET, in particular, in an N channel DMOSFET.

摘要翻译： 提供了能够实现具有低导通电阻和低反馈电容的MOSFET的技术，其中即使在沟道层的浅结形成在平面型MOSFET中时也可以防止沟道层的穿通。 P型多晶硅用于平面型MOSFET中的栅电极，特别是在N沟道DMOSFET中。

公开(公告)号：US07211862B2

公开(公告)日：2007-05-01

申请号：US11249335

申请日：2005-10-14

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727

摘要： A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n−-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n−-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n−-type single crystal silicon layer.

摘要翻译： 一种半导体器件，其中在不增加电池间距的情况下改善功率MISFET的雪崩承受能力。 在半导体器件中，具有p型导电的杂质离子，例如， B离子从接触孔的底部引入以形成p型半导体区域，其设置在p + +型半导体区域下方并与p + >型半导体区域和n + O型单晶硅层，并且其杂质浓度低于p + + H +型半导体区域。 在p型半导体区域下方设置的n型半导体区域形成n型半导体区域，与p型半导体区域接触，杂质浓度越低 比n + - 型单晶硅层。

公开(公告)号：US06885061B2

公开(公告)日：2005-04-26

申请号：US10827295

申请日：2004-04-20

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p− type semiconductor region and p− type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n− type single crystal silicon layer 1B is ρ (Ω·cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.148 ρ.

摘要翻译： 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个栅极线区域中同时形成p +型半导体区域和p-O +型场限制环 杂质离子注入步骤使其与形成有栅极引出电极的沟槽接触。 在形成时，假设设置在沟槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则CHSP 设定为满足以下等式：CHSP <= 3.80 + 0.148 rho。

公开(公告)号：US08604563B2

公开(公告)日：2013-12-10

申请号：US13486738

申请日：2012-06-01

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L27/088

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。

公开(公告)号：US08232610B2

公开(公告)日：2012-07-31

申请号：US12873495

申请日：2010-09-01

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L27/088

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。