公开(公告)号：US20070045727A1

公开(公告)日：2007-03-01

申请号：US11508860

申请日：2006-08-24

申请人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi

发明人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/66712 ,  H01L29/7806

摘要： A technology capable of realizing a MOSFET with low ON-resistance and low feedback capacitance, in which the punch through of a channel layer can be prevented even when the shallow junction of the channel layer is formed in a planar type MOSFET is provided. A P type polysilicon is used for a gate electrode in a planar type MOSFET, in particular, in an N channel DMOSFET.

摘要翻译： 提供了能够实现具有低导通电阻和低反馈电容的MOSFET的技术，其中即使在沟道层的浅结形成在平面型MOSFET中时也可以防止沟道层的穿通。 P型多晶硅用于平面型MOSFET中的栅电极，特别是在N沟道DMOSFET中。

公开(公告)号：US07847347B2

公开(公告)日：2010-12-07

申请号：US12724409

申请日：2010-03-15

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US20090224315A1

公开(公告)日：2009-09-10

申请号：US12463962

申请日：2009-05-11

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US20080035990A1

公开(公告)日：2008-02-14

申请号：US11836574

申请日：2007-08-09

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/772

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 在半导体衬底10中形成栅沟槽13。 栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16。 栅电极16的一部分从半导体基板10突出，并且在突出部分的侧壁部分上形成侧壁24。 主体沟槽25形成为与相邻的栅电极16对准。 在栅电极16的表面上并在体沟槽25的表面上形成钴硅化物膜28。 使用SAC技术形成插头34。

公开(公告)号：US07968939B2

公开(公告)日：2011-06-28

申请号：US12954877

申请日：2010-11-28

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US07544568B2

公开(公告)日：2009-06-09

申请号：US11836574

申请日：2007-08-09

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US08405145B2

公开(公告)日：2013-03-26

申请号：US13153348

申请日：2011-06-03

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US07759730B2

公开(公告)日：2010-07-20

申请号：US12463962

申请日：2009-05-11

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US08741699B2

公开(公告)日：2014-06-03

申请号：US13479360

申请日：2012-05-24

申请人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

发明人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

IPC分类号： H01L21/332

CPC分类号： H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

摘要： Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

摘要翻译： 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

公开(公告)号：US20110233665A1

公开(公告)日：2011-09-29

申请号：US13153348

申请日：2011-06-03

申请人： HITOSHI MATSUURA ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： HITOSHI MATSUURA ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.