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公开(公告)号：US09207744B2
公开(公告)日：2015-12-08
申请号：US14088880
申请日：2013-11-25
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li , Jiangtao Wang
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3206
Abstract: The present invention discloses a method for adjusting device power consumption including: grouping multiple devices into at least one device group, setting a group power consumption ceiling threshold (PCCT) for the device group, and setting a device PCCT for each device in the group; obtaining current total power consumption of the group, and when the current total power consumption of the group exceeds the group PCCT, determining whether current power consumption of each device in the group exceeds the device PCCT of the device; when the current power consumption of each device exceeds the device PCCT of the device, reducing power consumption of each device to the device PCCT of the device; and when current power consumption of a device exceeds a device PCCT of the device, setting a new PCCT for the device, and reducing power consumption of the device to/or less than the new PCCT.
Abstract translation: 本发明公开了一种用于调整设备功耗的方法，包括：将多个设备分组成至少一个设备组，为设备组设置组功耗上限阈值（PCCT），并为组中的每个设备设置设备PCCT; 获取组的当前总功耗，当组的当前总功耗超过组PCCT时，确定组中每个设备的当前功耗是否超过设备的设备PCCT; 当每个设备的当前功耗超过设备的设备PCCT时，将每个设备的功耗降低到设备的设备PCCT; 并且当器件的当前功耗超过器件的器件PCCT时，为器件设置新的PCCT，并将器件的功耗降低到或小于新的PCCT。
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公开(公告)号：US20150117096A1
公开(公告)日：2015-04-30
申请号：US14532196
申请日：2014-11-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11B7/004 , G11B11/10504 , G11B11/10597 , G11C13/0004 , G11C13/003 , G11C13/0064 , G11C2013/0066
Abstract: A write operation method for a phase change memory (PCM) is disclosed. The method includes when a PCM performs a write operation, generating a corresponding voltage pulse signal according to to-be-written data, and applying the voltage pulse signal to a phase change material included in a phase change storage unit corresponding to the to-be-written data and applying the voltage pulse signal to a voltage divider resistor serially connected to the phase change material; comparing voltage values at both ends of a sampling resistor with a threshold voltage to generate an indicator value; determining, according to the indicator value, whether data that is stored in the phase change storage unit and is corresponding to the indicator value is the same as the to-be-written data; and skipping writing if the same; or writing if different, thus reducing the delay time of writing data into the phase change storage unit.
Abstract translation: 公开了一种用于相变存储器（PCM）的写入操作方法。 该方法包括当PCM执行写入操作时，根据写入的数据产生相应的电压脉冲信号，并将电压脉冲信号施加到相应于待更改的相变存储单元中的相变材料 写入数据并将电压脉冲信号施加到串联连接到相变材料的分压电阻器; 将采样电阻两端的电压值与阈值电压进行比较，生成指标值; 根据指标值确定存储在相变存储单元中并且与指示符值相对应的数据是否与待写入数据相同; 并跳过写作如果相同; 或如果不同则进行写入，从而减少将数据写入相变存储单元的延迟时间。
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公开(公告)号：US20150113198A1
公开(公告)日：2015-04-23
申请号：US14584698
申请日：2014-12-29
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li , Yulin Zheng
IPC: G06F12/06
CPC classification number: G06F13/4234 , G06F13/4027
Abstract: A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip. Thereby, a memory capacity of the existing processor increases while a processing capability does not increase.
Abstract translation: 提供了一种内存扩展系统和方法。 该系统包括处理器，扩展存储器，扩展芯片和多个处理器安装位置，其中在每个处理器安装位置提供存储器安装位置; 多处理器安装位置通过QuickPath Interconnect（QPI）接口连接，处理器安装在至少一个处理器安装位置，至少其中一个处理器安装位置用作扩展安装位置; 延长芯片安装在至少一个扩展安装位置; 并且扩展内存安装在内存安装位置。 在这种存储器扩展系统中，扩展芯片安装在另一个处理器安装位置，使得现有处理器可以通过使用扩展芯片访问扩展芯片的扩展存储器。 因此，现有处理器的存储器容量增加，而处理能力不增加。
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公开(公告)号：US20150019918A1
公开(公告)日：2015-01-15
申请号：US14474502
申请日：2014-09-02
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
CPC classification number: G06F11/1088 , G06F11/0766 , G06F11/108 , G06F11/1092 , G06F11/167 , G06F2201/845 , G06F2212/262 , G06F2212/7208
Abstract: A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.
Abstract translation: 提供了一种用于减少读延迟的方法和装置。 该方法包括：当与读取命令对应的一个或多个闪存芯片处于忙状态时，将处于忙状态的一个或多个闪存芯片读取的数据设置为错误的数据; 根据从其他闪存芯片读取的错误数据和数据，重建正确的数据，并报告正确的数据。 通过使用本发明，从闪存芯片读取的数据被设置为错误的数据，并且根据从其他闪存芯片读取的错误数据和数据获得重建的正确数据。 以这种方式，当闪存芯片处于忙状态时，可以避免擦除操作或写入操作阻止读取操作，从而有效地减少延迟并提高存储系统的性能。
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公开(公告)号：US20140298087A1
公开(公告)日：2014-10-02
申请号：US14307141
申请日：2014-06-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
IPC: G06F11/14
CPC classification number: G06F11/1469 , G06F11/1076 , G06F11/2082 , G11B20/1879 , G11B20/1883 , G11B2020/1893
Abstract: This invention discloses a hard disk data recovery method, apparatus, and system. The method includes: recording a logical block address corresponding to erroneous data if an error is discovered when data is read from the hard disk; performing a recovery operation for data at a first physical block address corresponding to the logical block address according to a preset algorithm to obtain recovered data; and sending an instruction of writing the recovered data into the logical block address to the hard disk so that the hard disk writes the recovered data into the logical block address according to the instruction, where the logical block address corresponds to a remapped second physical block address. Therefore, the method repairs an erroneous sector or a bad block of the hard disk quickly and improves efficiency of repairing the erroneous sector of the hard disk or the bad block of the hard disk.
Abstract translation: 本发明公开了一种硬盘数据恢复方法，装置和系统。 该方法包括：当从硬盘读取数据时，如果发现错误，则记录与错误数据相对应的逻辑块地址; 根据预设算法对与逻辑块地址对应的第一物理块地址对数据执行恢复操作，以获得恢复的数据; 并发送将恢复的数据写入到硬盘的逻辑块地址的指令，使得硬盘根据指令将恢复的数据写入逻辑块地址，其中逻辑块地址对应于重新映射的第二物理块地址 。 因此，该方法快速地修复硬盘的错误扇区或坏块，并且提高修复硬盘的错误扇区或硬盘的坏块的效率。
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Patent Agency Ranking
公开(公告)号：US20140082251A1
公开(公告)日：2014-03-20
申请号：US14083826
申请日：2013-11-19
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
IPC: G06F13/40
CPC classification number: G06F1/3278 , G06F1/3253 , G06F13/4018 , G06F13/4022 , G06F13/4282 , G06F2213/0026 , Y02D10/157
Abstract: Embodiments of the present invention disclose a PCI express device, and a link energy management method and device. The method includes: obtaining, by a first device, adjustment information for performing adjustment processing on a current rate and/or bit width of a PCI express link; stopping, by the first device, data sending, and clearing a master enable bit of a configuration space command register of a second device at an opposite end of the link, so that the second device stops data sending after current data sending is finished; performing, by the first device, adjustment processing on the rate and/or bit width of the link according to the adjustment information; resuming, by the first device, the data sending, and resetting the master enable bit, so that the first device and the second device send and receive data again at a rate and/or bit width that is obtained after the adjustment processing.
Abstract translation: 本发明的实施例公开了一种PCI快速装置和链路能量管理方法和装置。 该方法包括：由第一设备获取用于对PCI Express链路的当前速率和/或比特宽度进行调整处理的调整信息; 由第一设备停止数据发送和清除链路相对端的第二设备的配置空间命令寄存器的主使能位，使得第二设备在当前数据发送完成之后停止数据发送; 通过第一设备对根据调整信息的链路的速率和/或比特宽度进行调整处理; 由第一设备恢复数据发送和复位主使能位，使得第一设备和第二设备以调整处理之后获得的速率和/或位宽再次发送和接收数据。
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公开(公告)号：US08543763B2
公开(公告)日：2013-09-24
申请号：US13715534
申请日：2012-12-14
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
CPC classification number: G06F12/08 , G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0659 , G06F3/0689 , Y02D10/154
Abstract: A redundant array of independent disks (RAID) controller includes a host interface, a processing core and a storage interface. The processing core is connected to a host and a hard disk. The RAID controller includes a halt control pin connected to the processing core and a control signal line in the host. The processing core receives a first level sent through the control signal line by the host when the hard disk is in a standby state, and halt an execution of a program in the processing core according to the first level; receives a second level sent through the control signal line by the host when the host receives a service request, and resume the execution of the program according to the second level; and receive the service request sent by the host and send the received service request to the hard disk to awaken the hard disk.
Abstract translation: 独立磁盘（RAID）控制器的冗余阵列包括主机接口，处理核心和存储接口。 处理核心连接到主机和硬盘。 RAID控制器包括连接到处理核心的停止控制引脚和主机中的控制信号线。 当硬盘处于待机状态时，处理核心通过主机接收通过控制信号线发送的第一电平，并根据第一电平停止执行处理核心中的程序; 当主机接收到服务请求时，接收由主机通过控制信号线发送的第二级，并根据第二级继续执行程序; 并接收主机发送的服务请求，并将接收到的服务请求发送到硬盘以唤醒硬盘。
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公开(公告)号：US09811497B2
公开(公告)日：2017-11-07
申请号：US14584698
申请日：2014-12-29
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li , Yulin Zheng
CPC classification number: G06F13/4234 , G06F13/4027
Abstract: A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip. Thereby, a memory capacity of the existing processor increases while a processing capability does not increase.
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公开(公告)号：US09542271B2
公开(公告)日：2017-01-10
申请号：US14474502
申请日：2014-09-02
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
CPC classification number: G06F11/1088 , G06F11/0766 , G06F11/108 , G06F11/1092 , G06F11/167 , G06F2201/845 , G06F2212/262 , G06F2212/7208
Abstract: A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.
Abstract translation: 提供了一种用于减少读延迟的方法和装置。 该方法包括：当与读取命令对应的一个或多个闪存芯片处于忙状态时，将处于忙状态的一个或多个闪存芯片读取的数据设置为错误的数据; 根据从其他闪存芯片读取的错误数据和数据，重建正确的数据，并报告正确的数据。 通过使用本发明，从闪存芯片读取的数据被设置为错误的数据，并且根据从其他闪存芯片读取的错误数据和数据获得重建的正确数据。 以这种方式，当闪存芯片处于忙状态时，可以避免擦除操作或写入操作阻止读取操作，从而有效地减少延迟并提高存储系统的性能。
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20.发明授权Method for backing up data in a case of power failure of storage system, and storage system controller 有权在存储系统电源故障和存储系统控制器的情况下备份数据的方法公开(公告)号：US09465426B2
公开(公告)日：2016-10-11
申请号：US14529477
申请日：2014-10-31
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yansong Li
CPC classification number: G06F1/30 , G06F11/1438 , G06F11/1461
Abstract: The present invention discloses a method for backing up data in a case of a power failure of a storage system including: when a power failure is detected, acquiring current refresh progress of a buffer in a storage system, an address, in the buffer, of data that is in the buffer and needs to be backed up to a non-volatile memory in the storage system, and a first time required for backing up the data; calculating, according to the current refresh progress of the buffer and the address of the data in the buffer, a second time for which the data can at least keep being not lost since a last refresh; and stopping refreshing the buffer, and backing up the data to the non-volatile memory, if the second time is greater than the first time.
Abstract translation: 本发明公开了一种在存储系统的电源故障的情况下备份数据的方法，包括：当检测到电源故障时，获取存储系统中的缓冲器的当前刷新进度，缓冲器中的地址， 数据位于缓冲区中，需要备份到存储系统中的非易失性存储器中，并且首次备份数据; 根据缓冲区的当前刷新进度和缓冲器中的数据的地址来计算，自上次刷新以来，数据可以至少保持不丢失的第二次; 并停止刷新缓冲区，并将数据备份到非易失性存储器，如果第二次大于第一次。
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