公开(公告)号：US20100177588A1

公开(公告)日：2010-07-15

申请号：US12687584

申请日：2010-01-14

申请人： Nakaba Kaiwa ,  Yutaka Ikeda ,  Hideyuki Yoko

发明人： Nakaba Kaiwa ,  Yutaka Ikeda ,  Hideyuki Yoko

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations.

摘要翻译： 校准电路包括具有与输出缓冲器的至少一部分基本相同的电路配置的复制缓冲器，响应于发出校准命令产生内部时钟的振荡器电路，以及控制电路 复制缓冲器与内部时钟同步。 根据本发明，由于执行不依赖于外部时钟的校准操作，即使当外部时钟的频率根据操作模式等而改变时，也可以保持恒定的时间段 给予一系列校准操作所需的单个调整步骤或恒定时间。

公开(公告)号：US20070148796A1

公开(公告)日：2007-06-28

申请号：US11585108

申请日：2006-10-24

申请人： Masayuki Nakamura ,  Hideyuki Yoko

发明人： Masayuki Nakamura ,  Hideyuki Yoko

IPC分类号： H01L21/66 ,  H01L23/58 ,  G01R31/26

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

摘要： AZQ calibration command internally generated from an external command different from a ZQ calbration command so as to automatically perform an additional ZQ calibration operation. A command interval between an imputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

摘要翻译： AZQ校准命令从内部由与ZQ calbration命令不同的外部命令生成，以便自动执行附加的ZQ校准操作。 有效地采用插补命令与下一命令之间的命令间隔来获得ZQ校准周期。 与ZQ校准命令不同的外部命令优选为自刷新命令。 添加ZQ校准操作可缩短ZQ校准操作之间的间隔。 因此，可以更精确地获得能够执行ZQ校准操作的ZQ校准电路。

公开(公告)号：US08400807B2

公开(公告)日：2013-03-19

申请号：US13595824

申请日：2012-08-27

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/02

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

摘要翻译： 一种包括第一半导体芯片，第二半导体芯片和控制器芯片的系统。 第一半导体芯片包括第一端子，第二端子，电耦合到第二端子的第一电路，电耦合到第一端子和第一电路的第二电路，以及电耦合到第二电路的第三电路。 第二半导体芯片包括第三端子，第四端子，电耦合到第四端子的第四电路，电耦合到第三端子和第四电路的第五电路，以及电耦合到第五电路的第六电路。

公开(公告)号：US08364434B2

公开(公告)日：2013-01-29

申请号：US12611598

申请日：2009-11-03

申请人： Hideyuki Yoko ,  Hiroki Fujisawa

发明人： Hideyuki Yoko ,  Hiroki Fujisawa

IPC分类号： G01R35/00

CPC分类号： H03F1/56 ,  H03F2200/366 ,  H03F2200/453 ,  H03F2200/456

摘要： To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.

摘要翻译： 包括具有与构成输出缓冲器的上拉电路基本相同的电路配置的第一复制缓冲器和具有与构成输出缓冲器的下拉电路基本相同的电路配置的第二复制缓冲器。 当发出第一校准命令ZQCS时，控制信号ACT1或ACT2被激活，并且对于第一副本缓冲器或第二副本缓冲器执行校准操作。 当发出第二校准命令ZQCL时，控制信号ACT1，ACT2都被激活，并且对于第一副本缓冲器和第二副本缓冲器都执行校准操作。

公开(公告)号：US20110084404A1

公开(公告)日：2011-04-14

申请号：US12923787

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Kayoko Shibata

发明人： Hideyuki Yoko ,  Kayoko Shibata

IPC分类号： H01L27/118

CPC分类号： H01L27/10897 ,  G11C5/04 ,  G11C5/063 ,  G11C29/12 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596

摘要： One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit.

摘要翻译： 一个接口芯片和多个芯片堆叠，并且这些半导体芯片通过多个通孔硅电极彼此电连接。 从驱动电路输出的数据信号通过硅通孔之一输入到芯片芯片。 输出选择电路通过激活多个三态反相器中的相应一个来选择贯穿硅通孔中的任何一个。 当反相器被激活时，主选择电路使测试信号从测试垫提供给接收器电路。 当逆变器失活时，来自任何一个通孔的数据信号被提供给接收器电路。

公开(公告)号：US07839159B2

公开(公告)日：2010-11-23

申请号：US11585108

申请日：2006-10-24

申请人： Masayuki Nakamura ,  Hideyuki Yoko

发明人： Masayuki Nakamura ,  Hideyuki Yoko

IPC分类号： G01R31/26

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

摘要： A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

摘要翻译： ZQ校准命令在内部从与ZQ校准命令不同的外部命令生成，以便自动执行附加的ZQ校准操作。 有效地采用输入命令和下一命令之间的命令间隔来获得ZQ校准周期。 与ZQ校准命令不同的外部命令优选为自刷新命令。 添加ZQ校准操作可缩短ZQ校准操作之间的间隔。 因此，可以更精确地获得能够执行ZQ校准操作的ZQ校准电路。

公开(公告)号：US20090097330A1

公开(公告)日：2009-04-16

申请号：US12285685

申请日：2008-10-10

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C7/00 ,  G11C11/21

CPC分类号： G11C7/1045 ,  G11C17/14 ,  G11C17/18

摘要： A fuse latch circuit starts a precharge operation for reading out a state of a fuse element when receiving an external command which is a command to reset an operation mode register (MRS reset command) after power-on, and reads out and latches the state of the fuse element after completion of the precharge operation.

摘要翻译： 当接收到作为上电之后复位运行模式寄存器（MRS复位指令）的命令的外部命令时，熔丝锁存电路开始预充电操作，以读出熔丝元件的状态，并读出并锁存 在预充电操作完成之后的熔丝元件。

公开(公告)号：US20090097329A1

公开(公告)日：2009-04-16

申请号：US12285165

申请日：2008-09-30

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4082

摘要： A semiconductor storage device includes: an input buffer that receives address data and command data; a first through-latch-type latch circuit that latches the command data in synchronism with a rising edge of a clock signal; and a second through-latch-type latch circuit that latches the address data in synchronism with a falling edge of the clock signal.

摘要翻译： 半导体存储装置包括：接收地址数据和命令数据的输入缓冲器; 第一通过锁存型锁存电路，与时钟信号的上升沿同步地锁存指令数据; 以及与时钟信号的下降沿同步地锁存地址数据的第二通过锁存型锁存电路。

公开(公告)号：US08547775B2

公开(公告)日：2013-10-01

申请号：US12923751

申请日：2010-10-06

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C5/02

摘要： The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

摘要翻译： 半导体存储器件包括分配有彼此不同的芯片识别信息的多个芯片芯片和控制多个芯片芯片的接口芯片。 接口芯片接收地址信息以指定存储器单元，并且通常将一部分地址信息作为芯片选择信息提供，以便与芯片识别信息进行比较以提供给多个核心芯片。 结果，由于控制器识别出地址空间被简单地放大，所以可以使用与根据现有技术的半导体存储器件相同的界面。

公开(公告)号：US08542516B2

公开(公告)日：2013-09-24

申请号：US13595793

申请日：2012-08-27

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/06

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

摘要翻译： 一种包括第一半导体芯片和第二半导体芯片的装置。 第一半导体芯片包括第一端子，第二端子，电耦合到第二端子的第一电路，电耦合到第一端子和第一电路的第二电路，以及电耦合到第二电路的第三电路。 第二半导体芯片包括第三端子，第四端子，电耦合到第四端子的第四电路，电耦合到第三端子和第四电路的第五电路，以及电耦合到第五电路的第六电路。