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公开(公告)号：US07571260B2
公开(公告)日：2009-08-04
申请号：US11541771
申请日：2006-10-03
摘要： A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.
摘要翻译： 微型计算机包括CPU，多个资源以及具有地址解码器的输出电路。 CPU向地址解码器输出地址信号。 地址解码器解码地址信号，并且输出电路根据解码的地址信号向至少一个资源输出选择信号。 当接收到选择信号时，每个资源都可由CPU写入。 当地址信号指示预定的地址时，输出电路一次向至少两个资源输出选择信号。 因此，可以一次将数据写入多个资源。 因此，CPU可以通过使用输出电路在减少的时间内将数据写入多个资源。
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公开(公告)号：US07554415B2
公开(公告)日：2009-06-30
申请号：US11640876
申请日：2006-12-19
CPC分类号： H03L1/026 , H03L1/027 , H03L7/0996 , H03L7/16
摘要： A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.
摘要翻译： 微型计算机包括用于通过使用CR电路产生具有频率的时钟信号的振荡器，用于根据来自外部源的数据输出相对于由振荡器产生的频率具有相乘频率的时钟信号的乘法器，温度检测单元 用于检测所述CR电路附近的温度，存储单元，用于存储使所述乘法器的输出中的时钟信号的倍频能够基于所述振荡器的温度相关振荡特性而具有恒定值的数据;以及 控制单元，用于根据与由温度检测单元检测到的温度相关的存储单元中的数据，将用于产生时钟信号的倍频的乘法值设置到乘法器。
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13.发明授权Semiconductor integrated circuit having multiple semiconductor chips with signal terminals 有权具有多个具有信号端子的半导体芯片的半导体集成电路公开(公告)号：US07466159B2
公开(公告)日：2008-12-16
申请号：US11586560
申请日：2006-10-26
IPC分类号： G01R31/02
CPC分类号： G11C5/066 , G01R31/31926 , G11C29/1201 , G11C29/48 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.
摘要翻译： 半导体集成电路包括：封装; 封装中的半导体芯片包括信号端子; 和连接信号端子的接线。 一个半导体芯片是包括探针端子和测试对象端子的测试对象芯片。 探头端子连接到外部端子，用于测试对象端子。 测试对象芯片还包括：用于连接探针端子和测试对象端子的公共布线; 用于连接/断开探针端子和公共布线的第一开关; 用于连接/断开测试对象端子和公共布线的第二开关; 以及用于中断要输入到探头端子的输入电路的测试信号的测试信号中断元件。
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公开(公告)号：US20080052555A1
公开(公告)日：2008-02-28
申请号：US11878799
申请日：2007-07-26
IPC分类号： G06F1/06
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.
摘要翻译： 微型计算机包括用于产生和输出主时钟信号的主振荡器，用于产生和输出子时钟信号的子振荡器，基于主时钟信号操作的中央处理单元，基于子时钟信号操作的信号输出电路 时钟信号并以预定间隔输出定时信号，以及电压监视电路，其基于子时钟信号进行操作，并且响应于定时信号间歇地执行电压监视功能。 子振荡器独立于主振荡器工作。
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公开(公告)号：US20060161763A1
公开(公告)日：2006-07-20
申请号：US11330237
申请日：2006-01-12
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译： 一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作 定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。 指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。 当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。
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公开(公告)号：US20050206461A1
公开(公告)日：2005-09-22
申请号：US11075882
申请日：2005-03-10
CPC分类号： G06F1/04 , G06F1/26 , H03K3/0315
摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.
摘要翻译： 集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。 内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。 内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。
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公开(公告)号：US20050188131A1
公开(公告)日：2005-08-25
申请号：US11007298
申请日：2004-12-09
CPC分类号： G06F13/24
摘要： A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.
摘要翻译： 单片微计算机包括逻辑电路，CPU和触发器，用于基于时钟信号将由逻辑电路提供的中断请求信号同步到CPU。 多芯片仿真装置包括分别用于仿真逻辑电路，CPU和触发器的功能的外围评估芯片，CPU评估芯片和装置。 当在开发中使用多芯片仿真装置来模拟单片机的功能时，用于模拟触发器的功能的装置同步中断请求信号以吸收由中断请求信号引起的延迟时间 由于外围评估芯片和CPU评估芯片之间的物理距离，使得仿真中的中断处理定时与单片机的实际操作中的中断处理定时相匹配。
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18.发明授权Semiconductor integrated circuit device forming power sources having different voltages for operating circuit blocks 有权形成具有用于操作电路块的不同电压的电源的半导体集成电路器件公开(公告)号：US06653880B2
公开(公告)日：2003-11-25
申请号：US09912059
申请日：2001-07-25
申请人： Hiroyuki Obata , Hideaki Ishihara
发明人： Hiroyuki Obata , Hideaki Ishihara
IPC分类号： H03K302
CPC分类号： G06F1/24
摘要： A microcomputer prevents an unnecessary signal from being outputted before the microcomputer is released from a reset state when the microcomputer includes a plurality of circuit blocks operating at different power source voltages. A reset signal transmitted to an input/output terminal unit of the microcomputer is generated by carrying out an OR operation between reset signals transmitted to a 3 V system circuit unit and a 5 V system circuit unit by an OR gate.
摘要翻译： 当微型计算机包括以不同电源电压工作的多个电路块时，微计算机防止在微计算机从复位状态释放之前输出不必要的信号。 发送到微计算机的输入/输出端子单元的复位信号是通过OR门进行发送到3V系统电路单元和5V系统电路单元的复位信号之间的“或”运算而产生的。
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公开(公告)号：US06304957B1
公开(公告)日：2001-10-16
申请号：US08202181
申请日：1994-02-25
申请人： Hideaki Ishihara , Kouichi Maeda
发明人： Hideaki Ishihara , Kouichi Maeda
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851
摘要： The microcomputer shall be offered which has realized more simplified peripheral circuits and more reduced price, besides being provided with the functions of timer, runaway monitor and backup logic. To that effect, the address register and the register are installed which have two areas each in correspondence with two tasks (CPU0 and CPU1) to perform a pipeline processing of the two tasks in parallel and in time division by changing over alternately the two areas of the address register and the register by means of task switching signal. Then, while composing one task (L-task) with a fix-looped program for which a branch instruction is prohibited, the L-task is embedded with a routine to execute a runaway monitor and a timer operation for the other task (A-task). Furthermore, in case where anything abnormal is detected by L-task about the processing of A-task and it is reset, the L-task will execute a backup sequence to obtain a failsafe of the system.
摘要翻译： 提供微型计算机，除了提供定时器，失控监视器和备用逻辑的功能外，还实现了更简化的外围电路，降低了价格。 为此，安装了地址寄存器和寄存器，它们具有两个对应于两个任务（CPU0和CPU1）的两个区域，以并行地并且通过分时地改变两个任务的两个区域来执行两个任务的流水线处理 地址寄存器和寄存器通过任务切换信号。 然后，当使用禁止分支指令的固定循环程序来组合一个任务（L任务）时，L任务被嵌入一个例程以执行失控监视器和另一任务的定时器操作（A- 任务）。 此外，如果L任务检测到任何关于A任务的处理的任何异常并且被复位，则L任务将执行备份序列以获得系统的故障保护。
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公开(公告)号：US5555020A
公开(公告)日：1996-09-10
申请号：US412202
申请日：1995-03-27
申请人： Hideaki Ishihara , Kiyoshi Tsuji , Akihiko Mochida
发明人： Hideaki Ishihara , Kiyoshi Tsuji , Akihiko Mochida
IPC分类号： A61B1/04 , G02B23/24 , H04N5/235 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/355 , H04N5/361 , H04N5/369 , H04N5/372 , H04N5/378 , H04N5/225
摘要： A solid-state imaging apparatus comprises a fast driving means that drives a solid-state imaging device at a high speed for the preservation time for one screen in a solid-state imaging device; that is, for one of time intervals corresponding to a plurality of divisions of a one-field period in a television signal mode, a fast transfer circuit for transferring pixel outputs of the solid-state imaging device at a high speed, field memories in which image signals sent from the fast transfer circuit are stored screen by screen, a selection output control circuit that reads the image signals stored screen by screen in the field memories by converting the time bases into the one for the one-field period in the television signal mode, and selectively outputs the plurality of read image signals depending on the state of a subject, and an adder for adding up the image signals selected by the selection output control circuit and providing an output image signal.
摘要翻译： 固态成像装置包括：快速驱动装置，其在固态成像装置中以高速度驱动一个屏幕的保存时间的固态成像装置; 也就是说，对于与电视信号模式中的一场周期的多个分割相对应的时间间隔中的一个，用于高速传送固态成像装置的像素输出的快速传送电路，其中 从快速传送电路发送的图像信号被屏幕逐个存储，选择输出控制电路通过将时基转换成电视信号中的一场期间的时基，从而在场存储器中通过屏幕读取存储的图像信号 模式，并且根据被摄体的状态选择性地输出多个读取图像信号，以及用于将由选择输出控制电路选择的图像信号相加并提供输出图像信号的加法器。
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