公开(公告)号：US07185244B2

公开(公告)日：2007-02-27

申请号：US10823581

申请日：2004-04-14

申请人： Hirotsugu Kojima ,  Teruo Kitamura

发明人： Hirotsugu Kojima ,  Teruo Kitamura

IPC分类号： G11C29/00 ,  H03L7/06 ,  H03L7/00

CPC分类号： G11C29/12015 ,  G11C7/1006 ,  G11C16/0433 ,  G11C16/0441 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2216/10

摘要： The invention provides a semiconductor integrated circuit for communication control and a wireless communication system using the same realizing reduction in the size of a chip and the size of a module by enabling trimming data to be written into a nonvolatile memory without increasing the number of external terminals. A rewritable nonvolatile memory is provided in a semiconductor integrated circuit, characteristics of circuits including an electronic part are measured and trimming data for correcting variations in the characteristics is stored in the nonvolatile memory. A pin and an interface circuit such as a test pin and a JTAG interface circuit which are originally provided for the semiconductor integrated circuit also serve as an input pin and an interface circuit for sending and storing the trimming data to the nonvolatile memory.

摘要翻译： 本发明提供了一种用于通信控制的半导体集成电路和使用该半导体集成电路的无线通信系统，其通过使修整数据能够被写入非易失性存储器而不增加外部端子的数量而实现芯片尺寸的减小和模块的尺寸 。 在半导体集成电路中提供可重写的非易失性存储器，测量包括电子部件的电路的特性，并且将用于校正特性变化的修整数据存储在非易失性存储器中。 最初为半导体集成电路提供的针脚和接口电路如测试针和JTAG接口电路也用作输入引脚和用于向微处理器发送和存储修整数据的接口电路。

公开(公告)号：US5400189A

公开(公告)日：1995-03-21

申请号：US33759

申请日：1993-03-18

申请人： Naoki Sato ,  Yasuhide Ouchi ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Yosuke Hori

发明人： Naoki Sato ,  Yasuhide Ouchi ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Yosuke Hori

IPC分类号： G11B5/035 ,  G11B20/10 ,  H03G5/00 ,  H03G5/16 ,  H03K5/159 ,  G11B5/09 ,  H03H7/30

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B5/035 ,  H03G5/165 ,  H03K5/159 ,  H03G5/005

摘要： A reproduction signal processing apparatus includes a memory circuit storing a predetermined pattern for deciding equalizing characteristics of an automatic equalizer in response to variation of a reproduction signal, a pattern converting circuit for converting the predetermined pattern outputted from the memory circuit into an equalization target pattern serving as a target of the equalization and correction by the automatic equalizer, an equalization error calculating circuit for producing an equalization error from the equalization target pattern and the equalization signal outputted from the automatic equalizer, and the automatic equalizer executing a partial response waveform process of the reproduction signal on the basis of the equalization error, for correcting the predetermined equalizing characteristics of the automatic equalizer by tracing the fluctuation of the reproduction signal. Thus, the equalization and correction tracing the variation of the equalizing characteristics of the automatic equalizer are executed, and also, the equalization and correction including the partial response waveform process are executed in the automatic equalizer.

摘要翻译： 再现信号处理装置包括：存储电路，存储用于响应于再现信号的变化而确定自动均衡器的均衡特性的预定模式;模式转换电路，用于将从存储器电路输出的预定模式转换成服务的均衡目标图形 作为自动均衡器的均衡和校正的目标，均衡误差计算电路用于从均衡目标模式产生均衡误差和从自动均衡器输出的均衡信号，并且自动均衡器执行部分响应波形处理 基于均衡误差的再现信号，用于通过跟踪再现信号的波动来校正自动均衡器的预定均衡特性。 因此，执行跟踪自动均衡器的均衡特性的变化的均衡和校正，并且在自动均衡器中执行包括部分响应波形处理的均衡和校正。

公开(公告)号：US5235538A

公开(公告)日：1993-08-10

申请号：US756884

申请日：1991-09-09

申请人： Norio Sumi ,  Hirotsugu Kojima ,  Junko Nakase

发明人： Norio Sumi ,  Hirotsugu Kojima ,  Junko Nakase

IPC分类号： G06F7/52 ,  G06F7/53 ,  G06F7/533

CPC分类号： G06F7/5332 ,  G06F7/523

摘要： The present invention features performance of operation processing between a signal obtained by converting a coefficient into a Booth code with a Booth encoder, storing the Booth code in a memory device in advance and reading out the stored Booth code for processing an input signal in a semiconductor operation device or a digital filter. As a result, a coding operation by a Booth encoder of the present invention will be performed only once at the time of rewriting a coefficient and will not be repeated, thereby enabling a high-speed operation and realizing reduction of circuit scale at the same time by using an encoded Booth code directly in an operation after a coefficient has been determined.

摘要翻译： 本发明的特征在于，将通过将系数转换为布斯编码而得到的信号与布斯编码器之间的操作处理的性能，将布斯代码预先存储在存储装置中，并读出存储的布斯码，以处理半导体中的输入信号 操作装置或数字滤波器。 结果，本发明的布斯编码器的编码操作在重写系数时将仅执行一次，并且不会重复，从而能够高速操作并同时实现电路规模的降低 通过在确定系数之后的操作中直接使用经编码的布斯代码。

公开(公告)号：US5027400A

公开(公告)日：1991-06-25

申请号：US394786

申请日：1989-08-16

申请人： Toru Baji ,  Yukio Nakano ,  Shiro Tanabe ,  Tetsuya Nakagawa ,  Hirotsugu Kojima

发明人： Toru Baji ,  Yukio Nakano ,  Shiro Tanabe ,  Tetsuya Nakagawa ,  Hirotsugu Kojima

IPC分类号： G06F17/30 ,  G09F27/00 ,  H04H9/00 ,  H04H20/28 ,  H04H20/76 ,  H04H60/31 ,  H04L12/00 ,  H04N7/16 ,  H04N7/173 ,  H04Q11/04

CPC分类号： H04H60/31 ,  G09F27/00 ,  H04H20/28 ,  H04H20/76 ,  H04N21/2543 ,  H04N21/4722 ,  H04N21/812 ,  H04N7/173 ,  H04N7/17336 ,  H04Q11/0478 ,  H04L2012/5638

摘要： A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscriber, a motion picture program data base, a commerical data base, a program transmitter for effecting accesses and transmissions of transmission programs onto transmission lines based on the setting of the main control unit, a commercial transmitter for accessing the commerical data base and for transmitting content thereof based on the setting of the main control unit, an image encoder for achieving a bandwidth compression on a video signal, a cell assembler for processing data to be transmitted onto a broadband transmission line so as to generate a cell of the data, and an asynchronous transfer mode exchange for delivering the cell to a subscriber system associated therewith. Each of the subscriber systems includes a network terminal, a terminal control unit, a decoder to decode the compressed video signal, and a television monitor.

公开(公告)号：US5880981A

公开(公告)日：1999-03-09

申请号：US695617

申请日：1996-08-12

申请人： Hirotsugu Kojima ,  Avadhani Shridhar

发明人： Hirotsugu Kojima ,  Avadhani Shridhar

IPC分类号： G06F7/00 ,  G06F7/544 ,  G06F9/305 ,  G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5443

摘要： The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

摘要翻译： 本发明考虑了改进的乘法器电路和方法，用于通过减少向乘法器的输入的转换次数来降低功耗。 通过重新排序乘法序列以利用重复输入值，乘法器的每个输入被固定为尽可能长的时间。 每个乘法的中间结果存储在单独的累加器中以获得最终的结果。 通过减少连接乘法器和包含累加器的数据寄存器文件的数据总线上的转换次数，能够进一步降低功耗。

公开(公告)号：US5519398A

公开(公告)日：1996-05-21

申请号：US135478

申请日：1993-10-13

申请人： Naoki Satoh ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Masao Hotta

发明人： Naoki Satoh ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Masao Hotta

IPC分类号： G11B5/09 ,  H03H17/02 ,  H03H17/06 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/36

CPC分类号： H03M1/0626 ,  H03M1/148 ,  H03M1/168 ,  H03M1/365

摘要： A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.

摘要翻译： 一种用于将模拟信号转换为数字信号并处理数字信号的信号处理装置。 特别地，通过使用低功耗的集成电路来实现用于高速执行处理的数字滤波器。 该信号处理装置包括用于将输入模拟信号与多个模拟参考电压的每个电压进行比较并根据模拟输入信号产生温度计代码Tc的电路，用于检测温度计代码Tc的变化点的解码器，以及 具有解码器的输出信号线作为字选择线的多个存储电路。 对应于每个字选择行的输入信号值与预定的滤波器系数的乘积存储在存储器电路的相应字中。 这些记忆被用作查找表。

公开(公告)号：US5222035A

公开(公告)日：1993-06-22

申请号：US706389

申请日：1991-05-28

申请人： Junko Nakase ,  Hirotsugu Kojima

发明人： Junko Nakase ,  Hirotsugu Kojima

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0286 ,  H03H17/06

摘要： When each sample is expressed by digital signals of 8 bits, 8 bits constituting each of the digital signals are divided into data of upper 5 bits including the most significant bit, and data of lower 4 bits including the least significant bit. These two data are respectively inputted to two filter circuit units, and are simultaneously subjected to a filtering process separately. Outputs of these two filter circuit units are inputted to an adder. In the adder, the output of the filter circuit unit being data of upper 5 bits subjected to a filtering process is weighted by a factor of 2 to the 4th power, and the weighted output is added to the output of the other filter circuit unit. The results of adding are outputted from the adder as signals obtained by the original digital signals of 8 bits subjected to the filtering process. Since the number of bits of individual data is made small by the division, the operation speed of computing elements and the number of times of recursive or multiple uses of computing elements are increased so that the circuit scale of the entire filter circuit can be reduced.

摘要翻译： 当每个采样由8位的数字信号表示时，构成每个数字信号的8位被分成包括最高有效位的高5位的数据和包括最低有效位的低4位的数据。 这两个数据分别输入到两个滤波电路单元，并分别同时进行滤波处理。 这两个滤波器电路单元的输出被输入到加法器。 在加法器中，作为经过滤波处理的高5位的数据的滤波器电路单元的输出被加权为2倍至4倍，加权输出相加于另一个滤波电路单元的输出。 从作为滤波处理的8位的原始数字信号得到的信号，从加法器输出相加结果。 由于通过除法使个别数据的位数变小，所以计算单元的运算速度和运算单元的递归或多次使用次数增加，从而可以减小整个滤波电路的电路规模。

公开(公告)号：US4945506A

公开(公告)日：1990-07-31

申请号：US324830

申请日：1989-03-17

申请人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

发明人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

IPC分类号： G06F17/10 ,  G06F17/16

CPC分类号： G06F17/16

摘要： A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

摘要翻译： 一种数字信号处理器，用于在包括多个数据项（x0，x1，x2，...，x7）的列向量输入信号和包括预定数量的系数数据项的矩阵之间计算矢量积，以便产生 列向量输出信号包括多个数据项（y0，y1，y2，...，y7）。 在第一周期中，列向量输入信号的前导数据x0存储在第一存储单元（Rin）中，而在该时间段内，在比第一周期更短的第二周期中，数据项（c0 顺序地读取构成矩阵的第一部分的行方向的c1，c1，c2，...，c7），使得两个数据项被相乘，从而将乘法结果存储在累加器中。 重复执行类似的数据处理，以便基于来自累加器的输出，获得由多个数据项（y0，y1，y2，...，y7）构成的列向量输出信号。