公开(公告)号：US5519398A

公开(公告)日：1996-05-21

申请号：US135478

申请日：1993-10-13

申请人： Naoki Satoh ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Masao Hotta

发明人： Naoki Satoh ,  Hirotsugu Kojima ,  Hideki Sawaguchi ,  Masao Hotta

IPC分类号： G11B5/09 ,  H03H17/02 ,  H03H17/06 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/36

CPC分类号： H03M1/0626 ,  H03M1/148 ,  H03M1/168 ,  H03M1/365

摘要： A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.

摘要翻译： 一种用于将模拟信号转换为数字信号并处理数字信号的信号处理装置。 特别地，通过使用低功耗的集成电路来实现用于高速执行处理的数字滤波器。 该信号处理装置包括用于将输入模拟信号与多个模拟参考电压的每个电压进行比较并根据模拟输入信号产生温度计代码Tc的电路，用于检测温度计代码Tc的变化点的解码器，以及 具有解码器的输出信号线作为字选择线的多个存储电路。 对应于每个字选择行的输入信号值与预定的滤波器系数的乘积存储在存储器电路的相应字中。 这些记忆被用作查找表。

公开(公告)号：US5966407A

公开(公告)日：1999-10-12

申请号：US251185

申请日：1994-05-31

申请人： Mitsuru Hiraki ,  Hirotsugu Kojima ,  Masaru Kokubo ,  Takafumi Kikuchi ,  Yuji Hatano ,  Kouki Noguchi ,  Masao Hotta

发明人： Mitsuru Hiraki ,  Hirotsugu Kojima ,  Masaru Kokubo ,  Takafumi Kikuchi ,  Yuji Hatano ,  Kouki Noguchi ,  Masao Hotta

IPC分类号： G06F13/40 ,  H04B3/00 ,  H04B25/00

CPC分类号： G06F13/4077 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.

摘要翻译： 一种总线驱动系统，包括具有数据信号线和控制信号线的n条母线，在发送端构成驱动电路的（n-1）个开关电路，用于预充电（n-2）母线的预充电电路和（n-1） 具有用于重新分配由总线构成的传输线的线电容的控制电路的总线，以及用于对第n总线进行预充电的预放电电路。 开关电路控制（n-2）总线，（n-1）总线和第n总线之间的导通和非导通，其中（n-2）个开关电路响应于（n-2） 位置信号和控制信号，而第（n-1）个开关电路响应于控制信号。 来自发送端的信号由接收端的检测电路经由传输线检测。

公开(公告)号：US07366489B2

公开(公告)日：2008-04-29

申请号：US10742813

申请日：2003-12-23

申请人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

发明人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC分类号： H04B1/06 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03D2200/0047 ,  H03K21/16

摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

摘要翻译： 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US5291135A

公开(公告)日：1994-03-01

申请号：US767667

申请日：1991-09-30

申请人： Masao Hotta ,  Hisashi Kado ,  Keiko Makie

发明人： Masao Hotta ,  Hisashi Kado ,  Keiko Makie

IPC分类号： G01R33/035

CPC分类号： G01R33/0356 ,  Y10S505/846

摘要： A multichannel weak magnetic field measuring system for neuromagnetic diagnosis is provided having a plurality of dc-SQUID magnetometers. Bias current setting circuits are provided for detecting an even harmonic component of the output across the terminals of the corresponding SQUID and automatically adjusting a DC bias current to the SQUID. Accordingly, the level of the component becomes a predetermined value. Circuitry is also included for equalizing the magnetic flux detection sensitivities of these dc-SQUID magnetometers. Abnormal operation detecting circuits are also provided for producing abnormal operation detected outputs when the level of the corresponding even harmonic component is smaller than a certain threshold value.

摘要翻译： 提供了具有多个dc-SQUID磁力计的用于神经磁性诊断的多通道弱磁场测量系统。 提供偏置电流设定电路，用于检测相应SQUID两端的输出的均匀谐波分量，并自动调整到SQUID的直流偏置电流。 因此，部件的电平成为规定值。 还包括电路用于均衡这些dc-SQUID磁力计的磁通检测灵敏度。 当相应的偶次谐波分量的电平小于某个阈值时，还提供异常运行检测电路用于产生异常运行检测输出。

公开(公告)号：US5113077A

公开(公告)日：1992-05-12

申请号：US588718

申请日：1990-09-27

申请人： Toshihiko Shimizu ,  Masao Hotta ,  Atsushi Moritani

发明人： Toshihiko Shimizu ,  Masao Hotta ,  Atsushi Moritani

IPC分类号： A61B6/03 ,  G01T1/17 ,  G01T1/20 ,  G01T1/29

CPC分类号： G01T1/17 ,  G01T1/2985

摘要： A radiation detection circuit integrates output currents of a plurality of X-ray CT scanner radiation detectors, which are combinations of scintillators and photodiodes, during a short period to convert them to charge information in order to collect data for reproducing a tomogram. A current amplifier is connected to the output terminal of the photo-diode, and an output current of the current amplifier is charged in an integration capacitor. In this manner, the radiation detection circuit enables reduction of the measurement period.

摘要翻译： 辐射检测电路在短时间内将作为闪烁体和光电二极管的组合的多个X射线CT扫描仪辐射检测器的输出电流进行积分，以将其转换为电荷信息，以便收集用于再现断层图像的数据。 电流放大器连接到光电二极管的输出端，并且电流放大器的输出电流在积分电容器中充电。 以这种方式，辐射检测电路能够减少测量周期。

公开(公告)号：US4939518A

公开(公告)日：1990-07-03

申请号：US248374

申请日：1988-09-23

申请人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

发明人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

IPC分类号： H03M1/12 ,  H03M1/20 ,  H03M1/36

CPC分类号： H03M1/206 ,  H03M1/1235 ,  H03M1/365

摘要： In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

摘要翻译： 在循环平均模数转换器中，具有多个电平的参考电压，每个电平被输入到闪存类型模数转换器中的多个比较器中的一个，周期性地被小电压移位，并且输出 为每个移位周期添加闪存型模数转换器，以获得输出数字信号。 分压电路的输出为N个电平提供参考电压，该电平周期性地受到小电压的限制。 N个参考电压被分成组，每个组由M个元件N / M组成，提供开关，每个选择一个参考电压一个接一个地为相关联的组N / M参考电压由这些开关选择 并提供给比较器。

公开(公告)号：US20110090103A1

公开(公告)日：2011-04-21

申请号：US12907629

申请日：2010-10-19

申请人： Masao Hotta ,  Tatsuji Matsuura

发明人： Masao Hotta ,  Tatsuji Matsuura

IPC分类号： H03M1/00

CPC分类号： H03M1/144

摘要： A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at the same time, correcting the bit values, and decides the bits lower than the predetermined bit based on the comparison result of one of the plurality of comparators.

摘要翻译： 公开了一种具有改进的精度并且能够进行高速操作的顺序比较型模数转换器（ADC），该模数转换器包括数/模转换器，其输出多个 根据多位数字信号的不同参考模拟信号，将输入模拟信号与多个参考模拟信号进行比较的多个比较器，以及从高位开始依次改变多位数字信号的位值的顺序比较控制电路 多个参考模拟信号中的至少一个变得更靠近输入模拟信号，并且基于比较结果从较高位确定比特值，并且同时校正所确定的较高比特值，其中顺序比较 控制电路基于多个比较结果将多位数字信号的位值判定为预定位 并且同时校正位值，并且基于多个比较器之一的比较结果来确定比预定位低的位。

公开(公告)号：US20080106453A1

公开(公告)日：2008-05-08

申请号：US11889620

申请日：2007-08-15

申请人： Masao Hotta ,  Tatsuji Matsuura

发明人： Masao Hotta ,  Tatsuji Matsuura

IPC分类号： H03M1/38

CPC分类号： H03M1/0675 ,  H03M1/144 ,  H03M1/361

摘要： An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.

摘要翻译： 模拟 - 数字转换器具有数模转换器，第一，第二和第三比较器，以及顺序比较寄存器和控制逻辑电路。 数模转换器产生模拟信号，第一，第二和第三比较器将输入模拟信号与彼此不同的第一，第二和第三模拟信号进行比较。 此外，顺序比较寄存器和控制逻辑电路控制从第一至第三比较器馈送到数模转换器的数字信号，并将数字信号作为数字值输出，该数字值通过使输入的模拟信号经受模拟 数字转换。

公开(公告)号：US4875048A

公开(公告)日：1989-10-17

申请号：US237757

申请日：1988-08-29

申请人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

发明人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/10

CPC分类号： H03M1/10 ,  H03M1/16 ,  H03M1/361

摘要： In a two-step parallel analog to digital converter of the type in which a first flash-type A/D converter determines the upper significant bits of a digital signal output having a desired number of bits and after a quantizing error of the first flash-type A/D converter has been determined from the difference between a value obtained by reconverting the upper significant bits to an analog value and the input analog value a second flash-type A/D converter subjects the quantizing error to A/D conversion to determine a digital output of the remaining lower significant bits, a gain correcting circuit is additionally provided to automatically establish a gain of a D/A converter for reconverting the upper significant bits to an analog value on the basis of a reference voltage applied to the first flash-type A/D converter. Moreover, a reference voltage generating circuit is additionally provided to establish upper and lower reference voltages of a second flash-type A/D converter for determining lower significant bits on the basis of the step voltage of the DAC output.

摘要翻译： 在两级并行模数转换器中，其中第一闪存型A / D转换器确定具有所需位数的数字信号输出的高有效位，并且在第一闪存型A / D转换器的量化误差之后， 已经根据通过将高有效位重新转换为模拟值而获得的值与输入模拟值之间的差确定了A / D转换器，第二闪存型A / D转换器将量化误差对A / D转换进行测量，以确定 附加提供增益校正电路以自动建立D / A转换器的增益，用于根据施加到第一闪存的参考电压将高有效位重新转换为模拟值 型A / D转换器。 此外，另外提供参考电压产生电路以建立第二闪存型A / D转换器的上限和下限参考电压，用于基于DAC输出的阶跃电压来确定较低有效位。

公开(公告)号：US4866444A

公开(公告)日：1989-09-12

申请号：US154086

申请日：1988-02-09

申请人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

发明人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/0809 ,  H03M1/365

摘要： A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.

摘要翻译： 闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。 一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。 转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。 当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于 生成特定输出的比较器所属的块的比较器。