公开(公告)号：US20050112859A1

公开(公告)日：2005-05-26

申请号：US10718881

申请日：2003-11-21

申请人： Yi-Lung Cheng ,  Shih-Chia Cheng

发明人： Yi-Lung Cheng ,  Shih-Chia Cheng

IPC分类号： H01L21/31 ,  H01L21/311 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure. The high etch rate ratio of insulator layer to silicon nitride allows the over etch cycle to be successfully accomplished without risk to underlying materials. A third phase of the anisotropic dry etch procedure selectively removes the silicon nitride layer and subsequently selectively removes the silicon rich, silicon oxide layer without damage to the now exposed conductive region, resulting in definition of the desired contact or via hole openings in the stack of insulator layers.

摘要翻译： 已经开发了在堆叠的绝缘体层中形成开口的方法，其特征在于由三层绝缘体复合材料构成的下面的蚀刻停止层。 首先在半导体衬底的导电区域上形成由富硅底层，氧化硅层和顶部氮化硅层组成的三层绝缘体复合体。 在沉积上覆绝缘体层之后，使用光致抗蚀剂形状作为蚀刻掩模，以允许通过各向异性干蚀刻程序的第一阶段在上覆绝缘体层中限定所需的接触或通孔形状，其中第一相干燥 蚀刻过程终止于氮化硅层的顶表面。 接下来，进行用于确保从三层绝缘体复合材料的表面完全去除上覆绝缘体层的过蚀刻程序作为各向异性干蚀刻工艺的第二阶段。 绝缘体层与氮化硅的高蚀刻速率比允许成功地实现过蚀刻循环，而不会对下面的材料造成风险。 各向异性干蚀刻过程的第三阶段选择性地去除氮化硅层，随后选择性地除去富含硅的氧化硅层，而不损害现在暴露的导电区域，导致定义了堆叠中的所需接触或通孔开口 绝缘体层。

公开(公告)号：US06713407B1

公开(公告)日：2004-03-30

申请号：US10284399

申请日：2002-10-29

申请人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Sez-An Wu ,  Yi-Lung Wang ,  Shin-Chi Lin

发明人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Sez-An Wu ,  Yi-Lung Wang ,  Shin-Chi Lin

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/0245 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76838

摘要： A method of depositing a plasma enhanced CVD metal nitride layer over an exposed copper surface in a semiconductor wafer manufacturing process to improve the metal nitride layer adhesion and to reduce copper hillock formation including providing a process surface which is an exposed copper surface; preheating the process surface; plasma sputtering the exposed copper surface in-situ to remove copper oxides; and, depositing a metal nitride layer in-situ according to a plasma enhanced CVD process at a selected deposition pressure to reduce plasma ion bombardment energy transfer and to suppress-copper hillock formation.

摘要翻译： 一种在半导体晶片制造工艺中在暴露的铜表面上沉积等离子体增强的CVD金属氮化物层的方法，以改善金属氮化物层的粘合性并减少铜的小丘形成，包括提供作为暴露的铜表面的工艺表面; 预热过程表面; 等离子体溅射暴露的铜表面以去除铜氧化物; 以及根据等离子体增强CVD工艺在选定的沉积压力下原位沉积金属氮化物层以减少等离子体离子轰击能量转移并抑制铜小丘形成。

公开(公告)号：US06703317B1

公开(公告)日：2004-03-09

申请号：US10356248

申请日：2003-01-30

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

IPC分类号： H01L21302

CPC分类号： H01L21/3105 ,  H01L21/02052 ,  H01L21/76826 ,  H01L21/76837 ,  Y10S438/906

摘要： A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

摘要翻译： 一种减少晶片工艺表面上的电荷不平衡的方法，包括提供具有包括最上面的第一材料层的工艺表面的半导体晶片; 根据包括喷射和洗涤中的至少一种的晶片清洁过程清洁工艺表面以在工艺表面产生电荷不平衡; 并且使所述工艺表面进行含氮等离子体处理以至少部分地中和所述电荷不平衡。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US07125802B2

公开(公告)日：2006-10-24

申请号：US10696432

申请日：2003-10-29

申请人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

发明人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

IPC分类号： H01L21/306

CPC分类号： C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

公开(公告)号：US20050272260A1

公开(公告)日：2005-12-08

申请号：US10861149

申请日：2004-06-04

申请人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US20050153537A1

公开(公告)日：2005-07-14

申请号：US10753637

申请日：2004-01-08

申请人： Yi-Lung Cheng ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ying-Lung Wang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826

摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.

摘要翻译： 公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。 将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。 氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。 复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

公开(公告)号：US20050121751A1

公开(公告)日：2005-06-09

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

公开(公告)号：US20050106858A1

公开(公告)日：2005-05-19

申请号：US10716818

申请日：2003-11-19

申请人： Yi-Lung Cheng ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Ying-Lang Wang

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831

摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.

摘要翻译： 公开了一种用于减少半导体器件中的金属扩散的方法。 在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。 在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到 电介质层。

公开(公告)号：US06802935B2

公开(公告)日：2004-10-12

申请号：US10103618

申请日：2002-03-21

申请人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B65G4907

CPC分类号： H01L21/67167 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/67196 ,  Y10S414/135

摘要： A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

摘要翻译： 本文公开了包括多个处理室的半导体处理装置和方法，其中在多个处理室中的每个处理室内发生至少一个半导体处理操作。 此外，本文公开的装置和方法包括机器人机构，用于在完成相关联的半导体处理操作时在多个处理室中旋转每个处理室。 这样的机器人机构可以包括多个机器人。 具体地说，这样的多个机器人可以包括配置在相关转盘上的六个机器人。