公开(公告)号：US09698262B2

公开(公告)日：2017-07-04

申请号：US15072130

申请日：2016-03-16

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Pawlak ,  Geert Eneman

IPC: H01L29/74 ,  H01L29/80 ,  H01L29/94 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/76 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/42356

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

公开(公告)号：US20210336002A1

公开(公告)日：2021-10-28

申请号：US17240694

申请日：2021-04-26

Applicant: IMEC VZW

Inventor： Roger Loo ,  Geert Eneman ,  Clement Porret

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

公开(公告)号：US20200212205A1

公开(公告)日：2020-07-02

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej PAWLAK ,  Liesbeth WITTERS ,  Geoffrey POURTOIS

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US20190081156A1

公开(公告)日：2019-03-14

申请号：US16119132

申请日：2018-08-31

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

Abstract: A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.

公开(公告)号：US09876080B2

公开(公告)日：2018-01-23

申请号：US15218922

申请日：2016-07-25

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/04 ,  H01L21/324 ,  H01L21/306 ,  H01L29/161 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

公开(公告)号：US09368498B2

公开(公告)日：2016-06-14

申请号：US14878012

申请日：2015-10-08

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

公开(公告)号：US09257539B2

公开(公告)日：2016-02-09

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

公开(公告)号：US20150179755A1

公开(公告)日：2015-06-25

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。