公开(公告)号：US09842777B2

公开(公告)日：2017-12-12

申请号：US15199535

申请日：2016-06-30

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Kurt Wostyn

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/16 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065 ,  H01L21/823412 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7849 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.

公开(公告)号：US11996459B2

公开(公告)日：2024-05-28

申请号：US17308453

申请日：2021-05-05

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

IPC: H01L29/00 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/311 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

公开(公告)号：US11056574B2

公开(公告)日：2021-07-06

申请号：US16696841

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Kurt Wostyn

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

Abstract: This disclosed technology generally relates to a semiconductor device. One aspect relates to a method of fabricating a stacked semiconductor including forming a semiconductor structure protruding above the substrate and a gate structure extending across the semiconductor structure. The semiconductor structure includes a lower channel layer formed of a first material, an intermediate layer formed of a second material and an upper channel layer formed of a third material. The method additionally includes forming oxidized end portions defining second spacers on end surfaces of an upper layer. And forming the oxidized end portions comprises oxidizing end portions of the upper channel layer at opposite sides of the gate structure using an oxidization process adapted to cause a rate of oxidation of the third material which is greater than a rate of oxidation of the first material, while first spacers cover intermediate end surfaces.

公开(公告)号：US10714595B2

公开(公告)日：2020-07-14

申请号：US16025048

申请日：2018-07-02

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Kurt Wostyn

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L21/311 ,  H01L29/786

Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.

公开(公告)号：US20190013395A1

公开(公告)日：2019-01-10

申请号：US16025048

申请日：2018-07-02

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Kurt Wostyn

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28255 ,  H01L21/31111 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.

公开(公告)号：US20180166558A1

公开(公告)日：2018-06-14

申请号：US15822497

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.