公开(公告)号：US20150021542A1

公开(公告)日：2015-01-22

申请号：US14510135

申请日：2014-10-09

Applicant: Industrial Technology Research Institute

Inventor： Heng-Yuan Lee ,  Pei-Yi Gu ,  Yu-Sheng Chen

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract translation: 提供了一种电阻随机存取存储器的存储单元及其制造方法。 该方法包括以下步骤。 形成第一电极。 在第一电极上形成金属氧化物层。 电极缓冲层叠层形成在金属氧化物层上，具有第一缓冲层和第二缓冲层，第一缓冲层位于第二缓冲层和金属氧化物层之间。 第二缓冲层与第一缓冲层的氧比第一缓冲层与来自金属氧化物层的氧反应更加强烈。 在电极缓冲层叠层上形成第二电极层。

公开(公告)号：US08823415B2

公开(公告)日：2014-09-02

申请号：US13645493

申请日：2012-10-04

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20 ,  H01L23/522

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二个输入端。

公开(公告)号：US10090033B2

公开(公告)日：2018-10-02

申请号：US15659572

申请日：2017-07-25

Applicant: Industrial Technology Research Institute

Inventor： Duan-Lee Tang ,  Yu-Sheng Chen ,  Ding-Yeong Wang

IPC: G11C11/00 ,  G11C11/16 ,  H04L9/32 ,  H04L9/08

Abstract: A physically-unclonable-function (PUF) circuit and the control method thereof are provided, and the control method can be applied to the magnetoresistive device. The control method includes providing a first energy to a plurality of magnetic-tunnel junction (MTJ) devices after initializing the MTJ devices to a resistance state, and determining whether the hamming weight of at least one of the MTJ devices which has a predetermined resistance state is within a predetermined range or not.

公开(公告)号：US20180182877A1

公开(公告)日：2018-06-28

申请号：US15608949

申请日：2017-05-30

Applicant: Industrial Technology Research Institute

Inventor： Li-Heng Lee ,  Yu-Sheng Chen

IPC: H01L29/778 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L21/02389 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/3083 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor structure is provided. The semiconductor structure includes a silicon substrate having a groove, an epitaxial layer disposed on the sidewalls of the groove, and a gate disposed above the epitaxial layer and electrically connected to the epitaxial layer. The sidewalls of the groove have a lattice direction of (111). The groove extends in a first direction. The semiconductor structure and its fabrication method make a complementary metal oxide semiconductor (CMOS) circuit and a high electron mobility transistor (HEMT) with high electron mobility, high breakdown voltage and heat resistance properties being capable of being integrated on the same silicon (100) substrate at the same time to enhance the ability of the system on chip to handle power and RF power signals.

公开(公告)号：US20180102155A1

公开(公告)日：2018-04-12

申请号：US15659572

申请日：2017-07-25

Applicant: Industrial Technology Research Institute

Inventor： Duan-Lee Tang ,  Yu-Sheng Chen ,  Ding-Yeong Wang

IPC: G11C11/16 ,  H04L9/32 ,  H04L9/08

CPC classification number: G11C11/161 ,  G11C7/20 ,  G11C7/24 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1695 ,  G11C2029/4402 ,  H04L9/0861 ,  H04L9/3278

Abstract: A physically-unclonable-function (PUF) circuit and the control method thereof are provided, and the control method can be applied to the magnetoresistive device. The control method includes providing a first energy to a plurality of magnetic-tunnel junction (MTJ) devices after initializing the MTJ devices to a resistance state, and determining whether the hamming weight of at least one of the MTJ devices which has a predetermined resistance state is within a predetermined range or not.

公开(公告)号：US09257641B2

公开(公告)日：2016-02-09

申请号：US14488300

申请日：2014-09-17

Applicant: Industrial Technology Research Institute

Inventor： Frederick T. Chen ,  Tai-Yuan Wu ,  Yu-Sheng Chen ,  Wei-Su Chen ,  Pei-Yi Gu ,  Yu-De Lin

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/122 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1683 ,  H01L45/1691

Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.

Abstract translation: 提供了包括层叠层的三维电阻存储器。 层叠层被封装在电介质层中，并且与封装介电层中的至少一个开口相邻。 至少一个L形可变电阻间隔件设置在邻近层叠层的开口的侧壁的至少一部分上。 电极层填充开口的剩余部分。

公开(公告)号：US20140035620A1

公开(公告)日：2014-02-06

申请号：US13645493

申请日：2012-10-04

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二输入端。