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    Continuous time linear equalization for current-mode logic with transformer
    12.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权
    具有变压器电流模式逻辑的连续时间线性均衡

    公开(公告)号：US09537685B2

    公开(公告)日：2017-01-03

    申请号：US15074530

    申请日：2016-03-18

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

    High-speed linear charge pump circuits for clock data recovery
    13.
    发明授权
    High-speed linear charge pump circuits for clock data recovery 有权

    公开(公告)号：US10804797B1

    公开(公告)日：2020-10-13

    申请号：US16284633

    申请日：2019-02-25

    Applicant: INPHI CORPORATION

    Inventor： Rajasekhar Nagulapalli ,  Simon Forey ,  Parmanand Mishra

    IPC: H02M3/07 ,  H03L7/089 ,  H04L7/033

    Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

    Compact high speed duty cycle corrector
    16.
    发明授权
    Compact high speed duty cycle corrector 有权

    公开(公告)号：US09882570B1

    公开(公告)日：2018-01-30

    申请号：US15389830

    申请日：2016-12-23

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03L7/08 ,  H03K5/156 ,  H03G3/20 ,  H04L27/01

    CPC classification number: H03L7/0807 ,  H03G3/20 ,  H03K5/1565 ,  H04L27/01

    Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    Loss of signal detection on CDR
    18.
    发明授权
    Loss of signal detection on CDR 有权
    CDR信号检测丢失

    公开(公告)号：US09515852B1

    公开(公告)日：2016-12-06

    申请号：US14842699

    申请日：2015-09-01

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Simon Forey

    IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20 ,  H04L25/02 ,  H04L7/033 ,  H04L12/26

    CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03M9/00 ,  H04B17/318 ,  H04L7/0083 ,  H04L7/0091 ,  H04L7/033 ,  H04L25/0262 ,  H04L27/01 ,  H04L43/04 ,  H04L43/16

    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供了一种用于检测信号损失的技术。 对输入数据流进行采样，并相应地生成恢复的时钟信号。 通过传输PLL产生比恢复的时钟信号高的频率的输出时钟信号。 将恢复的时钟信号的频率与输出时钟信号的分频进行比较。 如果恢复的时钟信号和输出时钟信号之间的差异大于阈值，则提供信号指示的丢失。 还有其它实施例。

    Continuous time linear equalization for current-mode logic with transformer
    20.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权
    具有变压器电流模式逻辑的连续时间线性均衡

    公开(公告)号：US09325319B1

    公开(公告)日：2016-04-26

    申请号：US14679934

    申请日：2015-04-06

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H03K19/094 ,  H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

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