公开(公告)号：US20210233832A1

公开(公告)日：2021-07-29

申请号：US16750213

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： Aastha Uppal ,  Je-Young Chang

IPC: H01L23/42 ,  H01L21/56

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US20250112106A1

公开(公告)日：2025-04-03

申请号：US18375337

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Tarek Gebrael ,  Darshan Ravoori ,  Matthew Magnavita ,  Aastha Uppal ,  Xiao Lu

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

Abstract: An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally coupled to a heat spreader or heat sink by vias through the second substrate. The backside heat spreader may enclose the backside IC die in an electrically conductive cage.

公开(公告)号：US12048123B2

公开(公告)日：2024-07-23

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US20200294884A1

公开(公告)日：2020-09-17

申请号：US16355596

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Javed Shaikh ,  Je-Young Chang ,  Kelly Lofgreen ,  Weihua Tang ,  Aastha Uppal

IPC: H01L23/38 ,  H01L35/10 ,  H01L35/16 ,  H01L35/18 ,  H01L35/30

Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

公开(公告)号：US10600699B2

公开(公告)日：2020-03-24

申请号：US15685772

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Shankar Devasenathipathy ,  Joseph B. Petrini

IPC: H01L21/66 ,  G01K7/22 ,  H01L23/498 ,  G01K1/02 ,  G01K1/14 ,  H01L23/427

Abstract: Embodiments of the present disclosure provide techniques and configurations for inspection of a package assembly with a thermal solution, in accordance with some embodiments. In embodiments, an apparatus for inspection of a package assembly with a thermal solution may include a first fixture to house the package assembly on the apparatus, and a second fixture to house at least a portion of a thermal solution that is to be disposed on top of the package assembly. The apparatus may further include a load actuator, to apply a load to a die of the package assembly, via the thermal solution, and a plurality of sensors disposed around the thermal solution and the package assembly, to perform in situ thermal and/or mechanical measurements associated with the application of the load to the die of the package assembly. Other embodiments may be described and/or claimed.

公开(公告)号：US11830783B2

公开(公告)日：2023-11-28

申请号：US16600107

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Divya Mani ,  Je-Young Chang

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/433 ,  H01L25/00 ,  H01L23/10 ,  H01L21/48 ,  H01L23/373 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L21/4875 ,  H01L23/10 ,  H01L23/3736 ,  H01L23/433 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49816

Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.