公开(公告)号：US11107908B2

公开(公告)日：2021-08-31

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Jasmeet S. Chawla ,  Christopher J. Wiegand ,  Kanwaljit Singh ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/775 ,  H01L29/10 ,  H01L29/739 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L21/285 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/47 ,  H01L29/78

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.

公开(公告)号：US10679782B2

公开(公告)日：2020-06-09

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: G11C11/16 ,  G11C11/18 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H03K19/18 ,  H03K19/23 ,  H01F41/32 ,  H01L27/22

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US10483026B2

公开(公告)日：2019-11-19

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  H01F10/32 ,  H01L43/10 ,  H01L43/08 ,  H03K19/16 ,  G11C11/16 ,  G11C11/155 ,  H03K19/18 ,  H01F10/26

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US20180240964A1

公开(公告)日：2018-08-23

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H01L43/06 ,  H03K19/18

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US10608167B2

公开(公告)日：2020-03-31

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18 ,  H01L43/06

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US20180240583A1

公开(公告)日：2018-08-23

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H03K19/18 ,  H01L43/12 ,  H01F41/32

CPC classification number: H01F10/3254 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/32 ,  H01L27/228 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/18 ,  H03K19/23

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US09911835B2

公开(公告)日：2018-03-06

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.