公开(公告)号：US20190049514A1

公开(公告)日：2019-02-14

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN P. O'BRIEN ,  KAAN OGUZ ,  CHRISTOPHER J. WIEGAND ,  MARK L. DOCZY ,  BRIAN S. DOYLE ,  MD TOFIZUR RAHMAN ,  OLEG GOLONZKA ,  TAHIR GHANI

IPC: G01R31/28 ,  G01R31/315 ,  H01L21/66 ,  G01R33/09 ,  H01L43/12

CPC classification number: G01R31/2831 ,  G01N24/10 ,  G01R31/315 ,  G01R33/098 ,  G01R33/60 ,  G01R35/00 ,  H01L22/14 ,  H01L43/12

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US20170148982A1

公开(公告)日：2017-05-25

申请号：US15126138

申请日：2014-06-26

Applicant: INTEL CORPORATION

Inventor： ELIJAH V. KARPOV ,  PRASHANT MAJHI ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ROBERT S. CHAU

IPC: H01L45/00

CPC classification number: H01L45/1206 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.

公开(公告)号：US20160351238A1

公开(公告)日：2016-12-01

申请号：US15116457

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  DAVID L. KENCKE ,  KAAN OGUZ ,  MARK L. DOCZY ,  SATYARTH SURI ,  ROBERT S. CHAU ,  CHARLES C. KUO ,  ROKSANA GOLIZADEH MOJARAD

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.

Abstract translation: 公开了用于形成具有环形接触的自旋转移力矩存储器（STTM）元件以减少临界电流要求的技术。 该技术降低给定磁性隧道结（MTJ）的临界电流要求，因为环形接触可以减小接触尺寸并增加局部电流密度，从而减少切换MTJ自由磁性层方向所需的电流。 在一些情况下，环形触点围绕防止电流通过的绝缘体层的至少一部分。 在这种情况下，电流流过环形触点并且在绝缘体层周围流动，以在流过自由磁性层之前增加局部电流密度。 绝缘体层可以包括介电材料，并且在一些情况下，是隧道材料，例如氧化镁（MgO）。 在某些情况下，对于给定的MTJ，实现至少10％的临界电流降低。