公开(公告)号：US20240364002A1

公开(公告)日：2024-10-31

申请号：US18139206

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/50 ,  H01Q1/2283 ,  H01Q9/045

Abstract: An antenna device includes integrated polymer nanocomposite (PNC) devices coupling an antenna on a substrate to both ground and signal terminals. The PNC devices may include PNC material between two electrodes. The PNC devices may be integrated into the antenna device with the substrate including at least one electrode of each of the PNC devices. One PNC device may convey a signal to or from the antenna, e.g., between the antenna and a signal terminal. Another PNC device may convey an electrostatic discharge (ESD) pulse to a ground terminal. The antenna device may include or be coupled to an integrated circuit (IC) die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US12080655B2

公开(公告)日：2024-09-03

申请号：US16368032

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Gianni Signorini ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

公开(公告)号：US20230299043A1

公开(公告)日：2023-09-21

申请号：US17698282

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Sonja Koller ,  Jan Proschwitz ,  Eduardo De Mesa

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

公开(公告)号：US20230299012A1

公开(公告)日：2023-09-21

申请号：US17698322

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

公开(公告)号：US20230197615A1

公开(公告)日：2023-06-22

申请号：US17557134

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Peter Baumgartner ,  Bernd Waidhas ,  Wolfgang Molzer ,  Klaus Herold ,  Joachim Singer ,  Michael Langenbuch ,  Thomas Wagner

IPC: H01L23/528 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/645 ,  H01L23/5226

Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

公开(公告)号：US20220415814A1

公开(公告)日：2022-12-29

申请号：US17355763

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L25/16 ,  H05K1/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the insulating material including a second conductive pathway electrically coupled to the TSV; and a second microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US11508637B2

公开(公告)日：2022-11-22

申请号：US16855418

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US11469213B2

公开(公告)日：2022-10-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Klaus Reingruber ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  H01L23/31

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US11374323B2

公开(公告)日：2022-06-28

申请号：US16473566

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoeckl ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US11211337B2

公开(公告)日：2021-12-28

申请号：US16703315

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.