公开(公告)号：US20230317705A1

公开(公告)日：2023-10-05

申请号：US17707366

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Bernd Waidhas ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti ,  Stefan Reif ,  Eduardo De Mesa ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/181 ,  H01L2225/06572 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1094 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

公开(公告)号：US20230317620A1

公开(公告)日：2023-10-05

申请号：US17708746

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/5383 ,  H01L23/15 ,  H01L24/16 ,  H01L21/4857 ,  H01L25/0655

Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.

公开(公告)号：US20230317582A1

公开(公告)日：2023-10-05

申请号：US17707183

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/14 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L25/0655 ,  H01L23/145 ,  H01L23/5381 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L21/4857

Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.

公开(公告)号：US20230299012A1

公开(公告)日：2023-09-21

申请号：US17698322

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

公开(公告)号：US20230299014A1

公开(公告)日：2023-09-21

申请号：US17698430

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna ,  Mohan Prashanth Javare Gowda

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/73 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

公开(公告)号：US20230299013A1

公开(公告)日：2023-09-21

申请号：US17698365

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna ,  Mohan Prashanth Javare Gowda

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

公开(公告)号：US20230282615A1

公开(公告)日：2023-09-07

申请号：US17685871

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Abdallah Bacha ,  Vishnu Prasad ,  Mohan Prashanth Javare Gowda ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz ,  Lizabeth Keser

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

公开(公告)号：US20230317681A1

公开(公告)日：2023-10-05

申请号：US17709481

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Vishnu Prasad ,  Bernd Waidhas ,  Eduardo De Mesa ,  Lizabeth Keser ,  Thomas Wagner ,  Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Jan Proschwitz

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3736 ,  H01L23/427 ,  H01L24/16 ,  H01L24/32 ,  H01L23/367 ,  H01L25/50 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/73203 ,  H01L2224/32245 ,  H01L2224/16146 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L24/14 ,  H01L24/73

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

公开(公告)号：US20230317618A1

公开(公告)日：2023-10-05

申请号：US17707157

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/14 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L25/0655 ,  H01L23/49816

Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.

公开(公告)号：US20230317551A1

公开(公告)日：2023-10-05

申请号：US17708890

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Vishnu Prasad ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser ,  Thomas Wagner ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz

IPC: H01L23/373 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L25/18 ,  H01L21/4896

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.