公开(公告)号：US10243034B2

公开(公告)日：2019-03-26

申请号：US15667333

申请日：2017-08-02

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid Hafez ,  Chia-Hong Jan

IPC: H01L49/02 ,  H01L27/06 ,  H01L23/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/07

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US20190006279A1

公开(公告)日：2019-01-03

申请号：US15748608

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Vadym Kapinus ,  Pei-Chi Liu ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/86 ,  H01L29/786

CPC classification number: H01L23/5228 ,  H01L21/86 ,  H01L27/0629 ,  H01L28/00 ,  H01L28/22 ,  H01L28/24 ,  H01L29/785 ,  H01L29/78657

Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

公开(公告)号：US10164115B2

公开(公告)日：2018-12-25

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H03D7/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H03D7/16 ,  H01L29/417

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US20180197966A1

公开(公告)日：2018-07-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US10008445B2

公开(公告)日：2018-06-26

申请号：US15110704

申请日：2014-02-11

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/78 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/525 ,  H01L27/112 ,  H01L29/66

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a greater z-height than a low-z portion of reduced current carrying capability disposed there between. A dielectric disposed over the low-z portion has a top surface planar with the high-z line portions to which fuse contacts may be landed. Fabrication of an embedded fuse may include undercutting a region of a first dielectric material disposed over a substrate. The undercut region is lined with a second dielectric material. A pair of electrically joined fuse ends are formed by backfilling the lined undercut region with a conductive material. In advantageous embodiments, fuse fabrication is compatible with high-K, metal gate transistor and precision polysilicon resistor fabrication flows.

公开(公告)号：US09520494B2

公开(公告)日：2016-12-13

申请号：US14913326

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/772 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US09324665B2

公开(公告)日：2016-04-26

申请号：US14142629

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/62 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/525

CPC classification number: H01L23/62 ,  H01L21/0217 ,  H01L21/32055 ,  H01L23/5256 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。 在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。 隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。 隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08993401B2

公开(公告)日：2015-03-31

申请号：US13927694

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

Abstract translation: 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。

公开(公告)号：US08681573B2

公开(公告)日：2014-03-25

申请号：US13870598

申请日：2013-04-25

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC: G11C7/22

CPC classification number: G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

Abstract: Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

Abstract translation: 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US11824002B2

公开(公告)日：2023-11-21

申请号：US16457712

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan ,  Jiansheng Xu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.