公开(公告)号：US20190279960A1

公开(公告)日：2019-09-12

申请号：US16349959

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Edvin Cetegen ,  Sandeep B. Sane

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H05K1/18

Abstract: Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

公开(公告)号：US20180090411A1

公开(公告)日：2018-03-29

申请号：US15279222

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

IPC: H01L23/367 ,  H01L23/373

CPC classification number: H01L23/3736 ,  H01L23/3733 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433

Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

公开(公告)号：US12261150B2

公开(公告)日：2025-03-25

申请号：US18399189

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US20250006691A1

公开(公告)日：2025-01-02

申请号：US18345695

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： George Robinson ,  Mohamed Elhebeary ,  Divya Jain ,  Viet Chau ,  Zewei Wang ,  Mukund Ayalasomayajula ,  Suraj Maganty ,  Tingting Gao ,  Andrew Wayne Carlson ,  Khalid Mohammad Abdelaziz ,  Craig Jerome Madison ,  Edvin Cetegen ,  Joseph Petrini

IPC: H01L23/00

Abstract: Compliant inserts for pin dipping processes are disclosed herein. An example apparatus disclosed herein includes a pin array to transfer material to a package substrate of an integrated circuit package, a cover plate, an elastic insert to be disposed between the cover plate and the pin array.

公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC: H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US11502008B2

公开(公告)日：2022-11-15

申请号：US16612618

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Nicholas S. Haehn ,  Edvin Cetegen ,  Shankar Devasenathipathy

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/10 ,  H01L23/538 ,  H01L23/58 ,  H01L23/00

Abstract: An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.

公开(公告)号：US20220102231A1

公开(公告)日：2022-03-31

申请号：US17032583

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L25/065

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.