公开(公告)号：US20180004688A1

公开(公告)日：2018-01-04

申请号：US15201370

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Emily CHUNG ,  Frank T. HADY ,  George VERGIS

IPC: G06F13/16 ,  G11C11/4076 ,  G06F13/42 ,  G11C11/4093 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/1066 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/32 ,  G11C2207/2254

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

公开(公告)号：US20240242740A1

公开(公告)日：2024-07-18

申请号：US18622813

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Phil GENG ,  Xiang LI ,  George VERGIS

IPC: G11C5/04 ,  H05K1/14 ,  H05K1/18

CPC classification number: G11C5/04 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: A retainer to inhibit movement of dual in-line memory modules (DIMMs) that are removably inserted into connectors attached to a printed circuit board (PCB) of a system. Inhibiting movement of the DIMMs, especially taller DIMMs, such as the higher height 2 U and 4 U DIMMs, mitigates the effects of operational vibration causing intermittent electrical discontinuity between DIMM and the PCB. The retainer inhibits movement of DIMMs at the connector component level by constraining all or a portion of top edges of DIMMs inserted into connectors. The retainer is implemented independently of the design of the system-level chassis. The retainer is shaped into any of a bracket or frame from multiple rigid horizontal, vertical and oblique members that permit airflow to the DIMMs and connectors retained therein.

公开(公告)号：US20230125412A1

公开(公告)日：2023-04-27

申请号：US18086639

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G11C7/10 ,  G11C7/22

Abstract: An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

公开(公告)号：US20230044892A1

公开(公告)日：2023-02-09

申请号：US17969518

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Xiang LI ,  Saravanan SETHURAMAN ,  George VERGIS ,  James A. McCALL

IPC: H05K1/11 ,  H01L25/18 ,  H05K1/18

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

公开(公告)号：US20220368047A1

公开(公告)日：2022-11-17

申请号：US17874111

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： George VERGIS ,  Xiang LI ,  Jun LIAO ,  Anthony M. CONSTANTINE ,  Min Suet LIM ,  Tongyan ZHAI ,  Konika GANGULY

IPC: H01R12/72 ,  G06F1/18 ,  H01R13/24 ,  H01R12/70

Abstract: An adapter card with compression-attached memory modules that can be inserted into a conventional vertical connector enables use of CAMMs in systems with vertical memory module connectors. In one example, an adapter card or riser card includes a printed circuit board (PCB) having an edge to be received by a dual-inline memory module (DIMM) connector. First conductive contacts proximate to the edge of the PCB are to be received by the DIMM connector, enabling the first conductive contacts to couple with contacts of the DIMM connector. Second conductive contacts on a face of the PCB are to couple with a first compression attached memory module (CAMM) via a first compression mount technology (CMT) connector. The adapter card includes conductive traces on or in the PCB between the first conductive contacts and the second conductive contacts to couple the CAMM with the DIMM connector.

公开(公告)号：US20220263262A1

公开(公告)日：2022-08-18

申请号：US17737243

申请日：2022-05-05

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01R13/24 ,  H01R13/652 ,  H01R13/04 ,  H01R12/71

Abstract: Examples described herein relate to a system that includes: a first signal pin and a first ground pin adjacent to the first signal pin. In some examples, the first signal pin comprises a first portion, a second portion, and a third portion. In some examples, the first ground pin comprises a first portion, a second portion, and a third portion, the second portion of the first signal pin comprises a vertical mount, the second portion of the first ground pin comprises a vertical mount, and the second portion of the first signal pin and the second portion of the first ground pin are arranged proximate one another.

公开(公告)号：US20220171669A1

公开(公告)日：2022-06-02

申请号：US17671903

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  George VERGIS ,  Myron LOEWEN ,  Matthew A. SCHNOOR

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/42 ,  G06F13/16

Abstract: An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.

公开(公告)号：US20210335414A1

公开(公告)日：2021-10-28

申请号：US17368732

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Chong J. ZHAO ,  James A. McCALL ,  Shigeki TOMISHIMA ,  George VERGIS ,  Kuljit S. BAINS

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

公开(公告)号：US20210224206A1

公开(公告)日：2021-07-22

申请号：US17222760

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  Kenneth FOUST ,  George VERGIS

IPC: G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G06F13/42 ,  G06F1/18 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US20210216238A1

公开(公告)日：2021-07-15

申请号：US17214770

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Bill NALE ,  George VERGIS

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.