公开(公告)号：US10964992B2

公开(公告)日：2021-03-30

申请号：US16186103

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Henning Braunisch ,  Gilbert W. Dewey ,  Telesphor Kamgaing ,  Hyung-Jin Lee ,  Johanna M. Swan

IPC: H01P1/213 ,  H01P3/127 ,  H01P5/103 ,  H01P3/10 ,  H01P3/16 ,  H01P5/107 ,  H01P3/12 ,  H01P5/08

Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

公开(公告)号：US20200295003A1

公开(公告)日：2020-09-17

申请号：US16354960

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US20200098926A1

公开(公告)日：2020-03-26

申请号：US16142940

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/51 ,  H01L27/11585

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

公开(公告)号：US20200058798A1

公开(公告)日：2020-02-20

申请号：US16461331

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.

公开(公告)号：US20200058705A1

公开(公告)日：2020-02-20

申请号：US16461334

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey

IPC: H01L27/24 ,  H01L27/092

Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.

公开(公告)号：US11676966B2

公开(公告)日：2023-06-13

申请号：US16354960

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/17 ,  H01L25/065 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/7851 ,  H01L2224/0401

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US11522059B2

公开(公告)日：2022-12-06

申请号：US15899590

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L23/29 ,  H01L29/24 ,  H01L29/22

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11437706B2

公开(公告)日：2022-09-06

申请号：US16369452

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L25/065 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L25/00

Abstract: Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US11222921B2

公开(公告)日：2022-01-11

申请号：US16635111

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.

公开(公告)号：US10818799B2

公开(公告)日：2020-10-27

申请号：US16461331

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66

Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.