公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

公开(公告)号：US20230413684A1

公开(公告)日：2023-12-21

申请号：US17843976

申请日：2022-06-18

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/10 ,  H01L27/228 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

公开(公告)号：US20230317729A1

公开(公告)日：2023-10-05

申请号：US17710584

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li ,  Ian Alexander Young ,  Julien Sebot ,  Punyashloka Debashis

IPC: H01L27/118 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11803 ,  H01L29/78391 ,  H01L29/66984

Abstract: In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

公开(公告)号：US20230086080A1

公开(公告)日：2023-03-23

申请号：US17482131

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  John J. Plombon ,  Hai Li ,  Kaan Oguz ,  Tanay A. Gosavi ,  Emily Walker

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: In one embodiment, an apparatus includes a magnet, a first structure, and a second structure. The first structure includes a first conductive trace and a magnetoelectric material. The first conductive trace is coupled to an input voltage terminal, and the magnetoelectric material is coupled to the first conductive trace and the magnet. The second structure includes a superlattice structure and a second conductive trace. The superlattice structure includes one or more topological insulator materials. Moreover, the superlattice structure is coupled to the magnet and the second conductive trace, and the second conductive trace is coupled to an output voltage terminal.

公开(公告)号：US12056596B2

公开(公告)日：2024-08-06

申请号：US16989371

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Hai Li ,  Ian A. Young

IPC: G06N3/063 ,  H03K3/03

CPC classification number: G06N3/063 ,  H03K3/0315

Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.

公开(公告)号：US20240224814A1

公开(公告)日：2024-07-04

申请号：US18148240

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  Hai Li

IPC: H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H03K19/18 ,  H10N52/80

CPC classification number: H10N50/85 ,  G11C11/161 ,  H01F10/3286 ,  H03K19/18 ,  H10N52/80

Abstract: Valleytronic magnetoelectric spin-orbit (MESO) logic devices comprise a charge-to-spin conversion input module that comprises a magnetoelectric capacitor. The input module converts a differential input voltage into a magnetization orientation of a ferromagnet possessing in-plane anisotropy (IPA) through exchange coupling between the IPA ferromagnet and the magnetoelectric layer of the capacitor. The magnetization orientation of the IPA ferromagnet can represent the logic state of the valleytronic MESO device. A spin-to-charge conversion output module comprises a ferromagnet possessing perpendicular magnetic anisotropy (PMA) and a 2D valleytronic material. The IMA and PMA ferromagnets are chirally-coupled through Dzaloshinskii-Moriya interaction, which causes the perpendicular magnetic orientation of the PMA ferromagnet to switch with the in-plane magnetization orientation of the IPA ferromagnet. The logic state of the device is read through injection of spin-polarized current from the PMA ferromagnet into the 2D valleytronic layer, which converts the injected spin-polarized current into a differential output current.

公开(公告)号：US20230320230A1

公开(公告)日：2023-10-05

申请号：US17709074

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22

CPC classification number: H01L43/10 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14 ,  H01L27/228 ,  H03K19/18

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

公开(公告)号：US20230317847A1

公开(公告)日：2023-10-05

申请号：US17711665

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Hai Li ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Julien Sebot ,  Raseong Kim ,  Chia-Ching Lin ,  Punyashloka Debashis

IPC: H01L29/78 ,  H01L43/10

CPC classification number: H01L29/78391 ,  H01L43/10

Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.

公开(公告)号：US20230189659A1

公开(公告)日：2023-06-15

申请号：US17550663

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Tanay A. Gosavi ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

CPC classification number: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  G06F7/58

Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.