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公开(公告)号：US09753530B2
公开(公告)日：2017-09-05
申请号：US14498135
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Herbert Hum , Eric Sprangle , Douglas Carmean , Rajesh Kumar
IPC: G06F1/24 , G06F15/177 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US11366511B2
公开(公告)日：2022-06-21
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US11054890B2
公开(公告)日：2021-07-06
申请号：US13954980
申请日：2013-07-31
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
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Patent Agency Ranking
公开(公告)号：US20210089113A1
公开(公告)日：2021-03-25
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
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公开(公告)号：US10386915B2
公开(公告)日：2019-08-20
申请号：US15256006
申请日：2016-09-02
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/24 , G06F9/00 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09910483B2
公开(公告)日：2018-03-06
申请号：US14154517
申请日：2014-01-14
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F9/30 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09874926B2
公开(公告)日：2018-01-23
申请号：US14498319
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Douglas Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09710391B2
公开(公告)日：2017-07-18
申请号：US13886467
申请日：2013-05-03
Applicant: Intel Corporation
Inventor： Wei Liu , Youfeng Wu , Christopher Wilkerson , Herbert Hum
IPC: G06F15/00 , G06F12/0888 , G06F9/45 , G06F9/30 , G06F9/38
CPC classification number: G06F12/0888 , G06F8/4442 , G06F9/30043 , G06F9/3826 , G06F9/383 , Y02D10/13
Abstract: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
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