公开(公告)号：US20230086499A1

公开(公告)日：2023-03-23

申请号：US17479155

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Uygar E. AVCI ,  Sudarat LEE ,  Carl NAYLOR ,  Tanay GOSAVI

IPC: H01L29/786 ,  H01L29/78

Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

公开(公告)号：US20220149192A1

公开(公告)日：2022-05-12

申请号：US17093452

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Carl NAYLOR ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Shriram SHIVARAMAN ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：US20190378972A1

公开(公告)日：2019-12-12

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.

公开(公告)号：US20190334079A1

公开(公告)日：2019-10-31

申请号：US16463821

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Justin S. BROCKMAN ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.

公开(公告)号：US20190165270A1

公开(公告)日：2019-05-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Sarah E. ATANASOV ,  Kevin P. O'BRIEN ,  Robert L. BRISTOL

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

公开(公告)号：US20190036010A1

公开(公告)日：2019-01-31

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian MAERTZ ,  Christopher J. WIEGAND ,  Daniel G. OEULLETTE ,  MD Tofizur RAHMAN ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Tahir GHANI ,  Brian S. DOYLE ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Kaan OGUZ

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US20190027679A1

公开(公告)日：2019-01-24

申请号：US16070415

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Christopher J. WIEGAND ,  MD Tofizur RAHMAN ,  Brian MAERTZ ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Tahir GHANI ,  Mark L. DOCZY

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.

公开(公告)号：US20240006481A1

公开(公告)日：2024-01-04

申请号：US17853547

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Sudarat LEE ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Chia-Ching LIN ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

公开(公告)号：US20230317783A1

公开(公告)日：2023-10-05

申请号：US17709365

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Carl H. NAYLOR ,  Uygar E. AVCI ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Scott B. CLENDENNING ,  Matthew V. METZ ,  Chia-Ching LIN ,  Sudarat LEE ,  Ashish Verma PENUMATCHA

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L29/78651

Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.